Two-wire communication systems and applications

• US 10,311,010 B2
• Filed: 10/16/2015
• Issued: 06/04/2019
• Est. Priority Date: 10/05/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kessler, Martin, Chavez, Miguel, Lahr, Lewis F., Hooper, William, Adams, Robert, Sealey, Peter
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US14/884,900
• Publication Number:
  US 20160041941A1
• Time in Patent Office: 1,327 Days
• Field of Search: 710110
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 19/4185 characterised by the network communication
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: H04B 2203/547 via DC power distribution
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02
• CPC Class Codes: H04L 12/4035 in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64
• CPC Class Codes: H04R 29/007 for public address systems public address systems per se H04R27/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Claims

1. A slave device for low-latency communication, comprising:

a slave node transceiver, including;

upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream device and to provide a second signal over the two upstream wires of the two-wire bus to the upstream device;

clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the slave node transceiver is based on the clock signal; and

power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream device.

2. The slave device of claim 1, wherein the slave node transceiver further includes downstream transceiver circuitry to provide a third signal downstream over two downstream wires of the two-wire bus toward a downstream device and to receive a fourth signal over the two downstream wires of the two-wire bus from the downstream device, the synchronization control frame is associated with downstream data in a superframe of the first signal, the downstream data includes multiple data slots, and data for a single peripheral device in communication with the slave node transceiver occupies two or more of the multiple data slots.

3. The slave device of claim 1, wherein the slave node transceiver further includes downstream transceiver circuitry to provide a third signal downstream over two downstream wires of the two-wire bus toward a downstream device and to receive a fourth signal over the two downstream wires of the two-wire bus from the downstream device, the second signal includes a synchronization response frame, the synchronization response frame is associated with upstream data in a superframe of the second signal, the upstream data includes multiple data slots, and data originating at a single peripheral device in communication with the slave node transceiver occupies two or more of the multiple data slots.

4. The slave device of claim 1, wherein the power circuitry is further to provide energy from the voltage bias to an energy storage device coupled to the slave node transceiver.

5. The slave device of claim 1, further comprising peripheral device communication circuitry to communicate with a microphone and a conferencing user interface element, wherein a user actuates the conferencing user interface element when the user wishes to provide audio from the microphone to another device coupled to the two-wire bus, and wherein the second signal includes data originating at the microphone when the conferencing user interface element is actuated.

6. The slave device of claim 1, wherein the upstream device is coupled to a wireless transceiver, the wireless transceiver is to receive voice calls, and the upstream transceiver circuitry is to receive data representative of the voice calls in the first signal.

7. The slave device of claim 1, further comprising peripheral device communication circuitry in communication with an antenna coupled to a vehicle, wherein the peripheral device communication circuitry communicates with the antenna via a wired connection.

8. The slave device of claim 7, wherein the upstream device is a master device located at a head unit of the vehicle.

9. The slave device of claim 1, further comprising peripheral device communication circuitry in communication with a sensor or an actuator at a joint of a robotic limb.

10. The slave device of claim 1, further comprising a receive mailbox and a transmit mailbox, wherein the slave node transceiver is to generate an interrupt for transmission to a host device coupled to a master node of the two-wire bus when data is provided to the transmit mailbox.

11. The slave device of claim 1, further comprising:

a first connector to couple to a microphone;

a second connector to couple to an audio receiving device; and

a conductor to transmit data between the first connector and the second connector;

wherein the slave node transceiver further includes peripheral device communication circuitry coupled to the conductor to receive the data transmitted between the first connector and the second connector, the data is included in the second signal, and the first connector, the second connector, the conductor, and the slave node transceiver are included in a microphone cable.

12. The slave device of claim 11, further comprising an analog to digital converter (ADC) to convert an analog microphone input received at the first connector to a digital signal, wherein the data transmitted between the first connector of the second connector includes the digital signal.

13. The slave device of claim 12, wherein the second connector is to provide the second signal and the analog microphone input to the audio receiving device.

14. The slave device of claim 12, further comprising a digital to analog converter (DAC) to convert the digital signal to an analog signal.

15. A master node transceiver for low-latency communication, comprising:

an Inter-Integrated Circuit Sound (I2S) receiver to receive an I2S signal from a host device, wherein the I2S signal provides clock information;

clock circuitry to generate a clock signal based on the clock information; and

downstream transceiver circuitry to provide a first signal downstream over two downstream wires of a two-wire bus toward a downstream device and to receive a second signal over the two downstream wires of the two-wire bus from the downstream device, wherein a preamble of a synchronization control frame of the first signal is based on the clock signal, and the downstream device generates its own clock signal based on the preamble;

wherein the master node transceiver is further to provide a voltage bias between the two downstream wires of the two-wire bus.

16. The master node transceiver of claim 15, wherein:

the first signal includes a first synchronization control frame and associated first downstream data and a second synchronization control frame and associated second downstream data;

the first downstream data includes a data slot having a particular index and including data for a first peripheral device coupled to the downstream device; and

the second downstream data includes a data slot having the particular index and including data for a second peripheral device, different from the first peripheral device, coupled to the downstream device.

17. The master node transceiver of claim 15, wherein the downstream device is coupled to a wireless transceiver, the wireless transceiver is to receive voice calls, and the downstream transceiver circuitry is to receive data representative of the voice calls in the second signal.

18. A host device, comprising:

Inter-Integrated Circuit Sound (I2S) transceiver circuitry to provide an I2S signal to a master node transceiver, wherein the master node transceiver is a master of a two-wire bus, the I2S signal provides clock information, the master node transceiver is to generate a clock signal based on the clock information, the master node transceiver is to provide a first signal downstream over two downstream wires of the two-wire bus toward a downstream device, a preamble of a synchronization control frame of the first signal is based on the clock signal, the downstream device is to generate its own clock signal based on the preamble, and the master node transceiver is further to provide a voltage bias between the two downstream wires of the two-wire bus;

Inter-Integrated Circuit (I2C) transceiver circuitry to receive a first I2C signal from the master node transceiver and to provide a second I2C signal to the master node transceiver; and

processing circuitry to generate data for the downstream device based on the first I2C signal, wherein the data for the downstream device is to be included in the second I2C signal and is to be transmitted to the downstream device by the master node transceiver over the two downstream wires of the two-wire bus.

19. The host device of claim 18, wherein the first signal includes data for at least one speaker coupled to the downstream device.

20. The host device of claim 18, wherein the host device includes a receive mailbox and a transmit mailbox, the host device is to generate an interrupt for transmission to the downstream device when data is provided to the transmit mailbox, and the downstream device is to generate an interrupt for transmission to the host device when data is to be provided to the receive mailbox.

21. The host device of claim 18, wherein the downstream device is coupled to an environmental sensor in a vehicle, and the processing circuitry is to generate a control instruction for a climate control system in the vehicle based on data from the environmental sensor transmitted to the host device via the master node transceiver and the two-wire bus.

22. A slave node transceiver for low-latency communication, comprising:

upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream device and to provide a second signal over the two upstream wires of the two-wire bus to the upstream device;

downstream transceiver circuitry to provide a third signal downstream over two downstream wires of the two-wire bus toward a downstream device and to receive a fourth signal over the two downstream wires of the two-wire bus from the downstream device;

clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the slave node transceiver is based on the clock signal;

peripheral device communication circuitry to provide the first signal or the second signal to a protocol analyzer, and wherein the downstream transceiver circuitry is disabled; and

power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream device.