Application processor including reconfigurable scaler and devices including the processor
First Claim
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1. An application processor comprising a reconfigurable hardware scaler, wherein the reconfigurable hardware scaler includes:
- a scaling technique selection register configured to select from different scaling techniques;
dedicated circuits each configured to perform a respective one of the different scaling techniques; and
a shared circuit configured to be shared by the dedicated circuits, wherein the shared circuit comprises a computation circuit configured to scale first pixels, and an analyzer circuit configured to analyze a pattern of second pixels relevant to the first pixels and to generate a selection signal that indicates a selection of one of the dedicated circuits; and
wherein the reconfigurable hardware scaler is configured to support the different scaling techniques depending upon a pattern of pixels to be processed and configured to, based, at least in part, upon the scaling technique selection register, perform the respective one of the different scaling techniques via the selected one of the dedicated circuits and the shared circuit.
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Abstract
An application processor includes a reconfigurable hardware scaler which includes dedicated circuits configured to perform different scaling techniques, respectively and a shared circuit configured to be shared by the dedicated circuits. One of the different scaling techniques is performed by one of the dedicated circuits and the shared circuit.
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Citations
17 Claims
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1. An application processor comprising a reconfigurable hardware scaler, wherein the reconfigurable hardware scaler includes:
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a scaling technique selection register configured to select from different scaling techniques; dedicated circuits each configured to perform a respective one of the different scaling techniques; and a shared circuit configured to be shared by the dedicated circuits, wherein the shared circuit comprises a computation circuit configured to scale first pixels, and an analyzer circuit configured to analyze a pattern of second pixels relevant to the first pixels and to generate a selection signal that indicates a selection of one of the dedicated circuits; and wherein the reconfigurable hardware scaler is configured to support the different scaling techniques depending upon a pattern of pixels to be processed and configured to, based, at least in part, upon the scaling technique selection register, perform the respective one of the different scaling techniques via the selected one of the dedicated circuits and the shared circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
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a memory configured to store an image comprising first pixels; an application processor communicatively coupled with the memory; wherein the application processor comprises; a direct memory access (DMA) controller configured to read the first pixels from the memory; and a scaling technique selection register configured to select from different scaling techniques; a reconfigurable hardware scaler configured to support the different scaling techniques depending upon a pattern of the first pixels to be processed, wherein the reconfigurable hardware includes; dedicated circuits configured to perform different scaling techniques, respectively, and a shared circuit configured to be shared by the dedicated circuits, wherein the shared circuit comprises a computation circuit configured to scale the first pixels, and an analyzer circuit configured to analyze a pattern of second pixels relevant to the first pixels and to generate a selection signal that indicates a selection of one of the dedicated circuits; and wherein, based, at least in part, upon the scaling technique selection register, one of the different scaling techniques is performed by the selected one of the dedicated circuits and the shared circuit. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A data processing system comprising:
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a system on chip; and a display, wherein the system on chip comprises; a memory configured to store an image comprising first pixels, and an application processor connected to the memory; wherein the application processor comprises; a direct memory access (DMA) controller configured to read the first pixels from the memory, and a scaling technique selection register configured to select from different scaling techniques; a reconfigurable hardware scaler configured to support the different scaling techniques depending upon a pattern of the first pixels to be processed; and wherein the reconfigurable hardware scaler comprises; dedicated circuits configured to perform different scaling techniques, respectively, and a shared circuit configured to be shared by the dedicated circuits, wherein the shared circuit comprises a computation circuit configured to scale the first pixels, and an analyzer circuit configured to analyze a pattern of second pixels relevant to the first pixels and to generate a selection signal that indicates a selection of one of the dedicated circuits, wherein, based, at least in part, upon the scaling technique selection register, one of the different scaling techniques is performed by the selected one of the dedicated circuits and the shared circuit. - View Dependent Claims (16, 17)
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Specification