Resistance change memory

• US 10,311,929 B2
• Filed: 12/08/2017
• Issued: 06/04/2019
• Est. Priority Date: 06/10/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation, SK Hynix Inc.
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation), SK Hynix Inc.
• Inventors: Aikawa, Hisanori, Kishi, Tatsuya, Nakatsuka, Keisuke, Inaba, Satoshi, Toko, Masaru, Hosotani, Keiji, Yi, Jae Yun, Suh, Hong Ju, Se Dong Kim
• Primary Examiner(s): Huang, Min
• Application Number:
  US15/835,988
• Publication Number:
  US 20180102156A1
• Time in Patent Office: 543 Days
• Field of Search: 365148
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Claims

1. A resistance change memory comprising:

a semiconductor substrate;

a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate;

an insulating layer covering the transistor;

a first conductive line connected to the first terminal and provided on the insulating layer;

a second conductive line provided on the insulating layer; and

a resistance change element connected between the second terminal and the second conductive line,

wherein the first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

2. The memory of claim 1, further comprising:

a sense amplifier connected to the second conductive line.

3. The memory of claim 2, further comprising:

a driver connecting the first conductive line to a ground terminal in a read operation using the sense amplifier.

4. The memory of claim 3, further comprising:

a third conductive line above the first conductive line; and

a switch element having a first end and a second end, the first end connected to the first conductive line,

wherein the driver is connected between the second end of the switch element and the third conductive line.

5. The memory of claim 3, further comprising:

a fourth conductive line above the second conductive line; and

a switch element connected between the second and fourth conductive lines.

6. The memory of claim 1, wherein

the control terminal is provided in the semiconductor substrate.

7. The memory of claim 1, wherein

the resistance change element comprises a first magnetic layer having invariable magnetization, a second magnetic layer having variable magnetization, and a nonmagnetic layer provided therebetween.