Cell bottom node reset in a memory array
First Claim
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1. A method, comprising:
- applying a cell bottom (CB) reset signal to a driver coupled with a memory array, the memory array comprising ferroelectric memory cells comprising cell bottom nodes and a cell plates opposite the cell bottom nodes, wherein each of the cell bottom nodes is configured to be electrically coupled with a respective digit line;
applying a voltage from a voltage source to a line of the driver based at least in part on applying the CB reset signal, wherein applying the voltage from the voltage source to the line activates word lines of the memory array and couples the digit lines to the cell bottom nodes.
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Abstract
Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.
7 Citations
20 Claims
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1. A method, comprising:
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applying a cell bottom (CB) reset signal to a driver coupled with a memory array, the memory array comprising ferroelectric memory cells comprising cell bottom nodes and a cell plates opposite the cell bottom nodes, wherein each of the cell bottom nodes is configured to be electrically coupled with a respective digit line; applying a voltage from a voltage source to a line of the driver based at least in part on applying the CB reset signal, wherein applying the voltage from the voltage source to the line activates word lines of the memory array and couples the digit lines to the cell bottom nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus, comprising:
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a memory array comprising ferroelectric memory cells comprising cell bottom nodes and cell plates opposite the cell bottom nodes, wherein each of the cell bottom nodes is configured to be electrically coupled with a respective digit line; and a driver coupled with the memory array, the driver comprising; a voltage source; a line coupled with the voltage source; and cell bottom (CB) reset line coupled with the voltage source and the line via a selection component, wherein the voltage source is configured to apply a voltage to the line based at least in part on a reset signal being applied to the CB reset line, wherein applying the voltage from the voltage source to the line activates word lines of the memory array and couples the digit lines to the cell bottom nodes. - View Dependent Claims (13, 14, 15, 16)
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17. An apparatus, comprising:
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a driver coupled with a memory array comprising ferroelectric memory cells comprising cell bottom nodes and cell plates opposite the cell bottom nodes, the driver comprising a voltage source, a cell bottom (CB) signal line, and a line; and a memory controller coupled with the driver, the memory controller operable to; initiate applying a CB reset signal to the driver; and initiate applying a voltage from the voltage source to the line based at least in part on initiating applying the CB reset signal, wherein applying the voltage from the voltage source to the line activates word lines of the memory array and couples the digit lines to the cell bottom nodes. - View Dependent Claims (18, 19, 20)
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Specification