Fin field effect transistor (FinFET) device structure and method for forming the same

• US 10,312,149 B1
• Filed: 11/13/2017
• Issued: 06/04/2019
• Est. Priority Date: 03/26/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chao, Yi-Cheng, Chang, Chai-Wei, Wu, Po-Chi, Li, Jung-Jui
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US15/810,831
• Publication Number:
  US 20190148241A1
• Time in Patent Office: 568 Days
• Field of Search: None
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.

Claims

1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming first plurality of fin structures and second plurality of fin structures in a first region and a second region of a substrate, respectively, wherein forming the first plurality of fin structures and the second plurality of fin structures comprises;

forming a third plurality of fin structures in the second region, wherein a density of the first plurality of fin structures in the first region is substantially equal to a density of a combination of the third plurality of fin structures and the second plurality of fin structure in the second region; and

removing the third plurality of fin structures to increase a spacing between the first plurality of fin structures and the second plurality of fin structures; and

forming an isolation structure on the substrate, wherein the isolation structure has a height difference between the first plurality of fin structures and the second plurality of fin structures.

2. The method as claimed in claim 1, wherein the height difference is in the second region.

3. The method as claimed in claim 1, wherein forming the isolation structure on the substrate comprises:

depositing a dielectric layer on the first plurality of fin structures and the second plurality of fin structures, wherein the dielectric layer has a height difference between the first plurality of fin structures and the second plurality of fin structures; and

performing an etching process to the dielectric layer to form the isolation structure.

4. The method as claimed in claim 3, wherein the dielectric layer has a first thickness which is measured from a top surface of the first plurality of fin structures to a top surface of the dielectric layer, and the first thickness is in a range from about 10 nm to about 50 nm.

5. The method as claimed in claim 1, further comprising:

forming a dummy gate structure on a middle portion of the first plurality of fin structures and the second plurality of fin structures;

removing the top portion of the first plurality of fin structures to form a cavity;

forming a source/drain (S/D) structure in the cavity and on the cavity; and

depositing an inter-layer dielectric (ILD) structure on the source/drain (S/D) structure and the dummy gate structure.

6. The method as claimed in claim 5, further comprising:

removing the dummy gate structure to form a trench;

forming a high-k dielectric layer in the trench; and

forming a metal gate electrode layer on the high-k dielectric layer.

7. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming a first plurality of fin structures and a second plurality of fin structures in a first region and a second region of a substrate, respectively, wherein a first pitch between two adjacent fin structures of the first plurality of fin structures is different from a second pitch between two adjacent fin structures of the second plurality of fin structures;

depositing a hard mask layer is over the first plurality of fin structures and the second plurality of fin structures;

depositing a dielectric layer adjacent to the hard mask layer, wherein a top surface of the dielectric layer is substantially level with a top surface of the hard mask layer;

removing the hard mask layer to expose top surfaces of the first plurality of fin structures and top surfaces of the second plurality of fin structures; and

removing a portion of the dielectric layer to form an isolation structure on the substrate.

8. The method as claimed in claim 7, wherein forming the first plurality of fin structures and the second plurality of fin structures in the first region and the second region, respectively comprises:

forming a pad layer on the substrate;

depositing the hard mask layer on the pad layer;

coating a photoresist layer on the hard mask layer;

patterning the photoresist layer to form a patterned photoresist layer;

patterning the hard mask layer and the pad layer by using the patterned photoresist layer as a mask to form the patterned hard mask layer and the patterned pad layer; and

etching a portion of the substrate by using the patterned hard mask layer and the patterned pad layer as a mask.

9. The method as claimed in claim 7, wherein forming the first plurality of fin structures and the second plurality of fin structures in the first region and the second region comprises:

forming third plurality of fin structures on the second region, wherein the number of the first plurality of fin structures in the first region is equal to a sum of a number of the third plurality of fin structures and the number of the second plurality of fin structure on the second region; and

removing the third plurality of fin structures, such that the number of the first plurality of fin structures in the first region is greater than the number of the second plurality of fin structures in the second region.

10. The method as claimed in claim 7, further comprising:

forming a dummy gate structure on a middle portion of the first plurality of fin structures and the second plurality of fin structures;

removing the top portion of the first plurality of fin structures to form a cavity;

forming a source/drain (S/D) structure in the cavity and on the cavity; and

forming an inter-layer dielectric (ILD) structure on the source/drain (S/D) structure and the dummy gate structure.

11. The method as claimed in claim 7, further comprising:

removing the dummy gate structure to form a trench;

forming a high-k dielectric layer in the trench; and

forming a metal gate electrode layer on the high-k dielectric layer.

12. The method as claimed in claim 7, further comprising:

forming a plurality of protruding structures between the two adjacent second plurality of fin structures in the second region, wherein the plurality of protruding structures are covered by the isolation structure.

13. A method for forming a multiple fin structures, comprising:

forming first plurality of fin structures in a first region and second plurality of fin structures in a second region of a substrate, wherein a density of the first plurality of fin structures is greater than a density of the second plurality of fin structures;

forming a plurality of protruding structures between two adjacent second plurality of fin structures in the second region;

forming a sacrificial layer on the first plurality of fin structures, the second plurality of fin structures and the plurality of protruding structures; and

removing an upper portion of the sacrificial layer to form an isolation structure on the substrate, wherein the plurality of protruding structures are covered by the isolation structure, and the first plurality of fin structures and the second plurality of fin structures extend above the isolation structure.

14. The method as claimed in claim 13, wherein forming the plurality of protruding structures comprises:

forming a third plurality of fin structures in the second region; and

removing an upper portion of the third plurality of fin structures to form the plurality of protruding structures.

15. The method as claimed in claim 14, wherein removing the upper portion of the third plurality of fin structures comprises:

removing the upper portion of the third plurality of fin structures, such that each of the plurality of protruding structures has a first height, and each of the first plurality of fin structures has a second height, and the first height is smaller than the second height.

16. The method as claimed in claim 13, wherein forming the first plurality of fin structures and the second plurality of fin structures in the first region and the second region, respectively comprises:

forming a pad layer on the substrate;

forming a hard mask layer on the pad layer;

forming a photoresist layer on the hard mask layer;

patterning the photoresist layer to form a patterned photoresist layer;

patterning the hard mask layer and the pad layer by using the patterned photoresist layer as a mask to form the patterned hard mask layer and the patterned pad layer; and

etching a portion of the substrate by using the patterned hard mask layer and the patterned pad layer as a mask.

17. The method as claimed in claim 13, further comprising:

forming a hard mask layer over the first plurality of fin structures and the second plurality of fin structures before forming the sacrificial layer on the first plurality of fin structures, the second plurality of fin structures and the plurality of protruding structures;

forming a dielectric layer on the first plurality of fin structures and the second plurality of fin structures; and

thinning the dielectric layer to expose a top surface of the hard mask layer, such that a top surface of the dielectric layer is level with the top a top surface of the hard mask layer.

18. The method as claimed in claim 17, further comprising:

removing the hard mask layer, such that a recess is formed over the first plurality of fin structures and the second plurality of fin structures; and

forming the sacrificial layer on the dielectric layer and the recess.

19. The method as claimed in claim 13, wherein the sacrificial layer has a first thickness which is measured from a top surface of each of the first plurality of fin structures to a top surface of the sacrificial layer, and the first thickness is in a range from about 10 nm to about 50 nm.

20. The method as claimed in claim 13, further comprising:

forming a dummy gate structure on a middle portion of the first plurality of fin structures and the second plurality of fin structures;

forming a source/drain (S/D) structure adjacent to the dummy gate structures; and

forming the inter-layer dielectric (ILD) structure on the S/D structure and the dummy gate structure.