Structure and formation method of chip package with antenna element

• US 10,312,203 B2
• Filed: 06/16/2017
• Issued: 06/04/2019
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiang, Yung-Ping, Wu, Nien-Fang, Hsiao, Min-Chien, Chiang, Yi-Che, Shih, Chao-Wen, Chang, Shou-Zen, Liu, Chung-Shi, Yu, Chen-Hua
• Primary Examiner(s): Junge, Bryan R
• Application Number:
  US15/625,678
• Publication Number:
  US 20180166405A1
• Time in Patent Office: 718 Days
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/25171 Fan-out arrangements
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/0075 : Stripline fed arrays H01Q21/065 takes precedence
• CPC Class Codes: H01Q 21/0087 : Apparatus or processes specially adapted for manufacturing antenna arrays manufacturing waveguides H01P11/00
• CPC Class Codes: H01Q 21/065 : Patch antenna array
• CPC Class Codes: H01Q 21/22 : Antenna units of the array energised non-uniformly in amplitude or phase, e.g. tapered array or binomial array
• CPC Class Codes: H01Q 9/045 : with particular feeding means for circular polarisation H01Q9/0428

Abstract

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

Claims

1. A method for forming a chip package, comprising:

forming a first conductive feature over a support substrate;

disposing a semiconductor die over the support substrate;

forming a first protective layer over the support substrate to surround the semiconductor die and the first conductive feature;

replacing the support substrate with a second protective layer;

disposing a conductive pin in the second protective layer;

forming an antenna element over the second protective layer, wherein the antenna element is electrically connected to the conductive pin; and

forming electrical connection between a conductive element of the semiconductor die and the antenna element through the first conductive feature.

2. The method for forming a chip package as claimed in claim 1, further comprising:

forming an opening in the second protective layer; and

forming a second conductive feature in the opening to be electrically connected to the first conductive feature, wherein the second conductive feature is electrically connected to the antenna element, and is electrically connected to the conductive element of the semiconductor die through the first conductive feature.

3. The method for forming a chip package as claimed in claim 1, further comprising:

forming an opening in the second protective layer;

printing a conductive paste over the second protective layer to fill the opening; and

curing the conductive paste to form a conductive layer, wherein the conductive layer has a first portion over the second protective layer and a second portion filling the opening, the first portion forms the antenna element, and the second portion forms a second conductive feature.

4. The method for forming a chip package as claimed in claim 3, wherein the conductive pin is installed in the opening before printing the conductive paste.

5. The method for forming a chip package as claimed in claim 4, wherein the conductive pin has a lower portion and an upper portion, the lower portion is between the upper portion and the first protective layer, and the lower portion is wider than the upper portion.

6. The method for forming a chip package as claimed in claim 1, further comprising:

forming an opening in the second protective layer; and

forming a conductive layer over the first protective layer, wherein the conductive layer has a first portion over the second protective layer and a second portion extending into the opening, the first portion forms the antenna element, and the second portion forms a second conductive feature.

7. The method for forming a chip package as claimed in claim 6, wherein the conductive layer is formed using an electroplating process, an electroless plating process, or a combination thereof.

8. The method for forming a chip package as claimed in claim 6,

wherein the conductive pin is installed in the opening before the conductive layer is formed, and the method further comprises:

forming a seed layer on the conductive pin before the conductive layer is formed.

9. The method for forming a chip package as claimed in claim 1, further comprising:

disposing a second semiconductor die over the support substrate before the first protective layer is formed, wherein after the first protective layer is formed, the first protective layer surrounds the second semiconductor die.

10. The method for forming a chip package as claimed in claim 1, wherein the second protective layer has a lower dielectric constant than that of the first protective layer.

11. The method for forming a chip package as claimed in claim 1, wherein the second protective layer has a lower dissipation factor than that of the first protective layer.

12. The method for forming a chip package as claimed in claim 1, further comprising forming a shielding element over the support substrate before the semiconductor die is disposed, wherein the semiconductor die covers a portion of the shielding element after the semiconductor die is disposed.

13. The method for forming a chip package as claimed in claim 12, wherein the shielding element is electrically isolated from the antenna element.

14. A method for forming a chip package, comprising:

forming a first conductive feature over a support substrate;

disposing a semiconductor die over the support substrate;

forming a first protective layer over the support substrate to surround the semiconductor die and the first conductive feature;

removing the support substrate;

forming a second protective layer over the first protective layer;

disposing a conductive pin in the second protective layer;

forming an antenna element over the second protective layer, wherein the antenna element is electrically connected to the conductive pin; and

forming electrical connection between a conductive element of the semiconductor die and the antenna element through the first conductive feature.

15. The method for forming a chip package as claimed in claim 14, further comprising:

forming an opening in the second protective layer; and

forming a second conductive feature in the opening to be electrically connected to the first conductive feature, wherein the second conductive feature is electrically connected to the antenna element, and is electrically connected to the conductive element of the semiconductor die.

16. The method for forming a chip package as claimed in claim 14, further comprising:

forming an opening in the second protective layer;

printing a conductive paste over the second protective layer to fill the opening; and

curing the conductive paste to form a conductive layer, wherein the conductive layer has a first portion over the second protective layer and a second portion filling the opening, the first portion forms the antenna element, and the second portion electrically connects the antenna element and the conductive element of the semiconductor die.

17. The method for forming a chip package as claimed in claim 16, wherein the conductive pin is installed in the opening before printing the conductive paste.

18. The method for forming a chip package as claimed in claim 14, wherein the conductive pin has a lower portion and an upper portion, the lower portion is between the upper portion and the first protective layer, and the lower portion is wider than the upper portion.

19. A method for forming a chip package, comprising:

forming a conductive feature over a support substrate;

disposing a semiconductor die over the support substrate;

forming a first protective layer to surround the semiconductor die and the conductive feature;

forming a second protective layer over the first protective layer;

disposing a conductive pin in the second protective layer;

forming an antenna element over the second protective layer, wherein the second protective layer is between the antenna element and the semiconductor die, and the antenna element is electrically connected to the conductive pin; and

forming electrical connection between a conductive element of the semiconductor die and the antenna element through the conductive feature.

20. The method for forming the chip package as claimed in claim 19, further comprising:

forming an opening in the second protective layer; and

forming a conductive layer over the second protective layer, wherein a first portion of the conductive layer extends into the opening, and a second portion of the conductive layer forms the antenna element.