Semiconductor package

• US 10,312,210 B2
• Filed: 04/10/2018
• Issued: 06/04/2019
• Est. Priority Date: 11/07/2014
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Huang, Ching-Liou, Yu, Ta-Jen
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Rahman, Khatib A
• Application Number:
  US15/949,868
• Publication Number:
  US 20180233476A1
• Time in Patent Office: 420 Days
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16105 : the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17104 : relative to the bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/26175 : Flow barriers
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32221 : the body and the item being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.

Claims

1. A semiconductor package, comprising:

a base having a device-attach surface;

a first conductive via and a second conductive via passing through the base;

a semiconductor die mounted on the base by a first conductive structure and a second conductive structure, wherein

the first conductive structure is in direct physical contact and partially overlaps with a first terminal surface of the first conductive via, and

the second conductive structure is in direct contact and fully overlaps with a second terminal surface of the second conductive via.

2. The semiconductor package of claim 1, wherein:

a first interface between the first conductive structure and the first terminal surface has a smaller area in plan view than the first terminal surface.

3. The semiconductor package of claim 1, wherein:

the device-attach surface comprises a base material, and wherein

the first conductive structure is in direct contact with the base material in the device-attach surface.

4. The semiconductor package of claim 3, wherein:

the second conductive structure is not in contact with the base material in the device-attach surface.

5. The semiconductor package of claim 1, further comprising:

an underfill material covering the first and second conductive vias and in direct contact with the device-attach surface.

6. The semiconductor package of claim 1,

wherein the first conductive structure comprises a conductive pillar and a conductive solder cap, and the conductive solder cap is in direct contact and partially overlaps with the first terminal surface of the first conductive via.

7. The semiconductor package of claim 1, wherein the first conductive structure is coupled to a power pad or ground pad of the semiconductor die.

8. The semiconductor package of claim 1, wherein the first conductive structure is a bump on trace structure and rectangular in a plan view.

9. A semiconductor package, comprising:

a base having a device-attach surface comprising a base material;

a first conductive via and a second conductive via passing through the base;

a first conductive structure in direct physical contact with a first terminal surface of the first conductive via and the base material in the device-attach surface, forming a first interface between the first conductive structure and the first terminal surface, wherein

the first conductive structure partially overlaps with the first conductive via such that, in plan view, the first interface has a smaller area than the first terminal surface; and

a second conductive structure is in direct contact and fully overlaps with the second conductive via.

10. The semiconductor package of claim 9, further comprising:

a semiconductor die mounted on the base by the first conductive structure, and

wherein the base has a solder-ball attach surface opposite to the device-attach surface, wherein the solder-ball attach surface is away from the semiconductor die.

11. The semiconductor package of claim 10, further comprising:

a solder-ball disposed on the solder-ball attach surface of the base and in contact with the first conductive via, wherein a second interface between the first conductive via and the solder-ball is opposite to the first interface.

12. The semiconductor package of claim 11, wherein the first interface is aligned to the device-attach surface of the base, and the second interface is not coplanar with the solder-ball attach surface of the base.

13. The semiconductor package of claim 11, wherein the solder-ball fully overlaps with the first conductive structure in plan view.

14. The semiconductor package of claim 11, wherein the solder-ball partially overlaps with the first conductive structure in plan view.