Semiconductor device

• US 10,312,233 B2
• Filed: 09/16/2015
• Issued: 06/04/2019
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Sugawara, Katsutoshi, Kagawa, Yasuhiro, Tanaka, Rina, Fukui, Yutaka
• Primary Examiner(s): Li, Meiya
• Application Number:
  US15/505,508
• Publication Number:
  US 20170271323A1
• Time in Patent Office: 1,357 Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0296 involving a specific disposition of the protective devices
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a base region of second conductivity type formed on a drift layer of first conductivity type, a source region of first conductivity type located in the base region, a trench passing through the base region and the source region and dividing cell regions in plan view, a protective diffusion layer of second conductivity type disposed on a bottom of the trench, a gate electrode embedded in the trench with a gate insulating film therebetween, a source electrode electrically connected to the source region, and a protective contact region disposed at each of positions of three or more cell regions and connecting the protective diffusion layer and the source electrode to each other. The protective contact regions are disposed such that a triangle whose vertices are centers of three protective contact regions located closest to one another is an acute triangle.

Claims

1. A semiconductor device, comprising:

a substrate;

a drift layer of a first conductivity type provided on said substrate;

a base region of a second conductivity type formed on said drift layer;

a source region of the first conductivity type located in said base region;

a trench passing through said base region and said source region, a bottom of the trench reaching said drift layer, the trench dividing the semiconductor device into a plurality of regions including cell regions and protective contact regions in a plan view;

a protective diffusion layer of the second conductivity type disposed on the bottom of said trench in said drift layer, the protective diffusion layer spanning an entire width of the trench in a cross-sectional view;

a gate insulating film formed on an inner wall of said trench;

a gate electrode embedded in said trench with said gate insulating film therebetween; and

a source electrode electrically connected to said source region,

wherein

three of the protective contact regions closest to one another are disposed at vertices of a triangle in the plan view, the vertices of the triangle corresponding to centers of the three of said-protective contact regions, the triangle being an acute triangle,

each of the protective contact regions connects said protective diffusion layer to said source electrode,

and

said cell regions and said protective contact regions each have a same width in the plan view.

2. The semiconductor device according to claim 1, wherein said trench is formed such that said cell regions are arranged in a lattice pattern.

3. The semiconductor device according to claim 1, wherein said trench is formed such that said cell regions are arranged in a staggered pattern.

4. The semiconductor device according to claim 1, wherein said trench is formed such that said cell regions are arranged in a comb pattern.

5. The semiconductor device according to claim 1, wherein said protective diffusion layer contains an impurity of the second conductivity type within a concentration range of 3×

10¹⁷ cm<sup>−

3</sup> or more and 1×

10¹⁸ cm<sup>−

3</sup> or less.

6. The semiconductor device according to claim 1, wherein each of said protective contact regions includes a groove having such a depth as to reach said protective diffusion layer.

7. The semiconductor device according to claim 1, wherein

said protective contact regions connect said protective diffusion layer and said source electrode to each other through an ohmic electrode, and

in each of said protective contact regions, said protective diffusion layer includes a high-concentration region having an impurity concentration of the second conductivity type of 5×

10¹⁸ cm<sup>−

3</sup> or more and 1×

10²¹ cm<sup>−

3</sup> or less in an area in contact with said ohmic electrode.

8. The semiconductor device according to claim 1, wherein said substrate comprises a wide-bandgap semiconductor including gallium-nitride-based semiconductor or diamond.

9. The semiconductor device according to claim 1, wherein said substrate comprises silicon carbide.