GaN transistors with polysilicon layers used for creating additional components
First Claim
Patent Images
1. A method of manufacturing an integrated circuit, the method comprising:
- depositing a channel layer over at least one buffer layer;
depositing a barrier layer over the channel layer, such that a two dimensional electron gas (2DEG) region is formed at an interface between the channel layer and the barrier layer;
forming an isolation region in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;
forming a gate structure for an enhancement mode device over the first portion of the 2DEG region;
depositing a first insulating layer over the gate structure;
forming a back gate over the second portion of the 2DEG region;
depositing a second insulating layer over the back gate;
depositing a polysilicon layer on the second insulating layer and etching the polysilicon layer, such that at least a portion of the etched polysilicon layer is disposed over the back gate;
doping the etched polysilicon layer to form at least one p-type region in the polysilicon layer;
depositing a third insulating layer on the etched polysilicon layer; and
forming at least one metal interconnect layer on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.
0 Assignments
0 Petitions
Accused Products
Abstract
A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
112 Citations
17 Claims
-
1. A method of manufacturing an integrated circuit, the method comprising:
-
depositing a channel layer over at least one buffer layer; depositing a barrier layer over the channel layer, such that a two dimensional electron gas (2DEG) region is formed at an interface between the channel layer and the barrier layer; forming an isolation region in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region; forming a gate structure for an enhancement mode device over the first portion of the 2DEG region; depositing a first insulating layer over the gate structure; forming a back gate over the second portion of the 2DEG region; depositing a second insulating layer over the back gate; depositing a polysilicon layer on the second insulating layer and etching the polysilicon layer, such that at least a portion of the etched polysilicon layer is disposed over the back gate; doping the etched polysilicon layer to form at least one p-type region in the polysilicon layer; depositing a third insulating layer on the etched polysilicon layer; and forming at least one metal interconnect layer on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. An integrated circuit comprising:
-
a channel layer disposed over at least one buffer layer; a barrier layer disposed over the channel layer, with a two dimensional electron gas (2DEG) region formed at an interface between the channel layer and the barrier layer; an isolation region disposed in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region; a gate structure for an enhancement mode device disposed over the first portion of the 2DEG region; a first insulating layer disposed over the gate structure; a back gate disposed over the second portion of the 2DEG region; a second insulating layer disposed over the back gate; a polysilicon layer disposed on the second insulating layer and over the back gate, the polysilicon layer including at least one p-type region; a third insulating layer disposed on the etched polysilicon layer; and at least one metal interconnect layer disposed on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
-
Specification