Display device

• US 10,312,268 B2
• Filed: 01/22/2018
• Issued: 06/04/2019
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: Yan, Tzu-Min, Lin, Ming-Chang, Lee, Kuan-Feng
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US15/876,383
• Publication Number:
  US 20180145094A1
• Time in Patent Office: 498 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display device is provided, which includes a substrate including a pixel region; a metal oxide semiconductor transistor disposed over the substrate and including: a metal oxide semiconductor layer, a first gate electrode overlapping with the metal oxide semiconductor layer; and a gate insulating layer disposed between the metal oxide semiconductor layer and the first gate electrode, and the gate insulating layer having a first opening, wherein the first opening and the pixel region overlap; a second insulating layer disposed over the metal oxide semiconductor layer and having a via and a second opening, wherein the second opening and the pixel region overlap; and a pixel electrode electrically connected to the metal oxide semiconductor layer through the via.

Claims

1. A display device, comprising:

a substrate comprising a pixel region and a driving circuit, wherein the pixel region is disposed adjacent to the driving circuit;

a metal oxide semiconductor transistor disposed over the substrate and comprising;

a metal oxide semiconductor layer,

a first gate electrode overlapping with the metal oxide semiconductor layer; and

a gate insulating layer disposed between the metal oxide semiconductor layer and the first gate electrode, and the gate insulating layer having a first opening, wherein the first opening and the pixel region overlap;

a second insulating layer disposed over the metal oxide semiconductor layer and having a via and a second opening, wherein the second opening and the first opening overlap; and

a pixel electrode electrically connected to the metal oxide semiconductor layer through the via.

2. The display device as claimed in claim 1, wherein the first opening further extends beyond the pixel region.

3. The display device as claimed in claim 2, wherein the first opening is adjacent to the driving circuit.

4. The display device as claimed in claim 1, further comprises a third insulating layer over the second insulating layer and in the second opening.

5. The display device as claimed in claim 4, wherein the third insulating layer is in contact with a sidewall of the second opening.

6. The display device as claimed in claim 4, wherein the third insulating layer is in contact with the substrate.

7. The display device as claimed in claim 1, further comprising a thin film transistor adjacent to the first opening.

8. The display device as claimed in claim 7, wherein the thin film transistor is a polysilicon transistor.

9. The display device as claimed in claim 8, further comprising a second gate electrode overlapping with a polysilicon layer of the polysilicon transistor.

10. The display device as claimed in claim 9, wherein the second gate electrode is disposed over the polysilicon layer.

11. The display device as claimed in claim 9, wherein the polysilicon layer is disposed over the second gate electrode.

12. The display device as claimed in claim 1, wherein the first gate electrode is disposed over the metal oxide semiconductor layer.

13. The display device as claimed in claim 1, wherein the metal oxide semiconductor layer is disposed over the first gate electrode.

14. The display device as claimed in claim 1, further comprising a source electrode and a drain electrode electrically connected to the metal oxide semiconductor layer.

15. The display device as claimed in claim 1, further comprising a shielding layer, wherein the metal oxide semiconductor layer overlaps the shielding layer.

16. The display device as claimed in claim 1, further comprising a display medium on the substrate.

17. The display device as claimed in claim 16, wherein the display medium comprises organic light-emitting diode, micro light-emitting diode, or quantum dot.

18. The display device as claimed in claim 1, being a flexible device.