Metal-insulator-metal capacitor structure

• US 10,312,318 B2
• Filed: 09/22/2015
• Issued: 06/04/2019
• Est. Priority Date: 09/22/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Cheng, Kangguo, Standaert, Theodorus E., Wang, Junli
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Mojaddedi, Omar F
• Application Number:
  US14/861,511
• Publication Number:
  US 20170084681A1
• Time in Patent Office: 1,351 Days
• Field of Search: 438239, 438243, 438244, 438250, 438253, 438254, 257 68, 257 71, 257154, 257301
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Claims

1. A method comprising:

forming at least one gate structure;

removing a material from the at least one gate structure to form a trench;

recessing an insulator material formed outside of the trench to form a ledge;

depositing a capacitor material within the trench and at edges of the trench;

etching the capacitor material to form a stepped feature having a plurality of steps at each of the edges of and inside the trench;

forming a first contact within the trench and in contact with a first conductive material of the capacitor material;

forming a second contact in contact with a second conductive material of the capacitor material at least partially outside of the trench by forming a contact trench in the insulator material to expose the capacitor material and filling the contact trench with a metal material; and

forming a capping material on top of the capacitor material,

wherein;

the first conductive material is a top electrode plate,

the second conductive material is a bottom electrode plate,

the bottom electrode plate is deposited on the ledge to increase surface contact area and forms a top step of the stepped feature at each of the edges of the trench,

the first contact is formed through the capping material and in direct contact with the top electrode plate within the trench,

the second contact is formed in direct contact with the top step of the stepped feature at each of the edges of the trench, and

the capping material comprises a low-k dielectric material and is formed to have a stepped configuration at each of the edges of the trench.

2. The method of claim 1, wherein the capacitor material deposited within the trench is formed on a high-k dielectric material of the at least one gate structure.

3. The method of claim 1, wherein the second contact is formed in direct contact with the bottom electrode plate on the increased surface contact area of the ledge.

4. The method of claim 1, wherein the capacitor material deposited within the trench is formed directly on a semiconductor substrate.

5. The method of claim 4, wherein:

the first conductive material is a top electrode plate;

the second conductive material is a center electrode plate; and

the depositing of the capacitor material further comprises;

forming a bottom electrode plate directly on the semiconductor substrate;

forming a first dielectric material on the bottom electrode plate;

forming the center electrode plate on the first dielectric material;

forming a second dielectric material on the center electrode plate; and

forming the top electrode plate on the second dielectric material.

6. The method of claim 5, wherein the center electrode plate is formed partly outside of the trench and on a ledge formed by recessing an insulator material outside of the gate structure.

7. The method of claim 6, wherein the second contact is formed on the center electrode plate at the edge or outside of the trench.

8. The method of claim 6, wherein the second contact is formed on the center electrode plate at the edge or outside of the trench, and a third contact is formed on the bottom electrode plate at the edge or outside of the trench.

9. The method of claim 1, further comprising forming an insulator material on top of the capping material.

10. The method of claim 9, wherein the insulator material is planarized to the level of the capping material.

11. The method of claim 10, further comprising forming the first contact through the insulator material.

12. The method of claim 11, wherein the first conductive material is contacted by the first contact at the center of the at least one gate structure.

13. The method of claim 12, further comprising forming the second contact with the second conductive material and the capping material at the edge or outside of the trench through the insulator material.

14. The method of claim 13, wherein the second conductive material is contacted by the second contact at the edge or outside of the at least one gate structure.

15. The method of claim 5, wherein the etching the capacitor material to form the stepped feature comprises removing a portion of the top electrode plate and a portion of the second dielectric material.