Bulk nanosheet with dielectric isolation

• US 10,312,323 B2
• Filed: 07/17/2017
• Issued: 06/04/2019
• Est. Priority Date: 10/21/2015
• Status: Active Grant

• Current Assignee: Tessera LLC (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Wang, Junli
• Primary Examiner(s): Niesz, Jamie C
• Application Number:
  US15/651,420
• Publication Number:
  US 20170317168A1
• Time in Patent Office: 687 Days
• CPC Class Codes: H01L 21/76213 introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Claims

1. A nanowire field effect transistor (FET) device, comprising:

a bulk semiconductor wafer comprising a dielectric isolation region in a top portion thereof, wherein the dielectric isolation region comprises a thermal oxide;

nanowire stacks on the bulk semiconductor wafer, wherein each of the nanowire stacks comprises alternating layers of a sacrificial material and a channel material, wherein portions of the channel material are released from the nanowire stacks in a channel region of the FET device and comprise nanowire channels of the FET device, and wherein a first layer in the nanowire stacks comprises the sacrificial material and is present on the bulk semiconductor wafer; and

a gate surrounding the nanowire channels in the channel region of the device, wherein the first layer in the nanowire stacks has an inverted triangular shape beneath the gate in the channel region of the device.

2. The nanowire FET device of claim 1, wherein the gate completely surrounds one or more of the nanowire channels in a gate-all-around configuration.

3. The nanowire FET device of claim 1, further comprising:

at least one dopant implanted into the top portion of the bulk semiconductor wafer.

4. The nanowire FET device of claim 3, wherein the at least one dopant is selected from the group consisting of:

fluorine, phosphorous, and combinations thereof.

5. The nanowire FET device of claim 3, wherein the at least one dopant is implanted into the top portion of the bulk semiconductor wafer at a dose of from about from about 5×

10¹⁵ atoms/cm² to about 5×

10¹⁶ atoms/cm², and ranges therebetween.

6. The nanowire FET device of claim 3, wherein the bulk semiconductor wafer has a thickness of from about 0.1 millimeters to about 0.75 millimeters, and ranges therebetween.

7. The nanowire FET device of claim 3, wherein the top portion of the bulk semiconductor wafer comprises a first thickness of from about 100 angstroms to about 500 angstroms, and ranges therebetween, of the bulk semiconductor wafer.

8. The nanowire FET device of claim 1, wherein the sacrificial material comprises silicon germanium and the channel material comprises silicon.

9. The nanowire FET device of claim 1, wherein the sacrificial material comprises silicon and the channel material comprises silicon germanium.

10. The nanowire FET device of claim 1, wherein the first layer in the nanowire stacks present on the bulk semiconductor wafer is thicker than other layers in the nanowire stacks.

11. The nanowire FET device of claim 10, wherein the first layer in the nanowire stacks has a thickness of from about 20 nanometers to about 35 nanometers, and ranges therebetween.

12. The nanowire FET device of claim 10, wherein the other layers in the nanowire stacks have a thickness of from about 10 nanometers to about 25 nanometers, and ranges therebetween.

13. The nanowire FET device of claim 1, further comprising:

spacers on opposite sides of the gate.

14. The nanowire FET device of claim 13, wherein the spacers offset the gate from source and drain regions of the device which comprise portions of the nanowire stacks extending out from the gate.

15. The nanowire FET device of claim 14, wherein the source and drain regions of the device comprise an in-situ doped epitaxial material selected from the group consisting of:

silicon, silicon carbide, and silicon germanium.

16. The nanowire FET device of claim 1, wherein the gate is a metal gate.

17. The nanowire FET device of claim 1, further comprising:

a gate dielectric separating the gate from the nanowire channels, wherein the gate dielectric is selected from the group consisting of;

hafnium oxide and lanthanum oxide.

18. The nanowire FET device of claim 1, wherein the bulk semiconductor wafer comprises a material selected from the group consisting of:

silicon, strained silicon, silicon carbide, germanium, silicon germanium, silicon-germanium-carbon, a silicon alloy, a germanium alloy, gallium arsenide, indium arsenide, indium phosphide, and combinations thereof.

19. The nanowire FET device of claim 1, wherein the dielectric isolation region is continuous along the top portion of the bulk semiconductor wafer beneath the nanowire stacks.