Gate structure of field effect transistor with footing

• US 10,312,352 B2
• Filed: 08/13/2018
• Issued: 06/04/2019
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Chen, Chang-Yin, Lin, Jr-Jung, Lin, Chih-Han, Chang, Yung Jung
• Primary Examiner(s): Carter, Michael
• Application Number:
  US16/102,502
• Publication Number:
  US 20180350958A1
• Time in Patent Office: 295 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Claims

1. A method, comprising:

providing a first semiconductor structure comprising a channel region;

forming an interfacial layer over the channel region;

forming a gate electrode layer over the interfacial layer;

etching the gate electrode layer for forming an anisotropic central region and redeposited footing regions of a gate electrode, wherein the footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

2. The method of claim 1, further comprising:

forming a source region and a drain region in the first semiconductor structure on opposite ends of the channel region.

3. The method of claim 1, wherein the providing the first semiconductor structure comprises:

forming a fin structure protruding from a surface of a substrate as the first semiconductor structure.

4. The method of claim 3, further comprising:

forming a gate spacer over a side wall of the gate electrode; and

forming a fin spacer over a side wall of an exposed portion of the fin structure on a side of the gate electrode and the gate spacer,

wherein the gate spacer and the fin spacer form an L-shaped cross-section, the L-shaped cross-section is substantially parallel to the surface of the substrate and the L-shaped cross-section has an indented corner conformal to the footing region.

5. The method of claim 3, further comprising:

removing the first semiconductor structure covered by the fin spacer; and

doping the first semiconductor structure to form a source extension region or a drain extension region in the first semiconductor structure on the side of the gate electrode.

6. The method of claim 2, wherein the forming the source region and the drain region in the first semiconductor structure on opposite ends comprises:

forming a source recess and a drain recess in the first semiconductor structure on the opposite ends of the channel region; and

epitaxially growing stressor material in the source recess and the drain recess to form the source region and the drain region, and the stressor material has a different lattice constant from that of a material of the channel region.

7. The method of claim 1, wherein the providing the first semiconductor structure comprises:

providing a semiconductor-on-insulator (SOI) substrate, wherein the SOI substrate comprises;

a handle substrate;

an insulator layer over the handle substrate; and

a semiconductor layer over the insulator layer as the first semiconductor structure.

8. A method, comprising:

forming a semiconductor structure including a fin protruding from a substrate;

forming a sacrificial gate electrode layer over the semiconductor structure;

etching the sacrificial gate electrode layer for forming a sacrificial gate electrode;

removing the sacrificial gate electrode; and

forming a gate electrode including a central region and footing regions to replace the sacrificial gate electrode, the central region including a gate dielectric, a work function metal layer and a fill metal; and

wherein the gate dielectric and the work function metal layer extend to the footing regions of the gate electrode, and the fill metal is free from extending to the footing regions of the gate electrode.

9. The method of claim 8, wherein the etching the sacrificial gate electrode layer for forming the sacrificial gate electrode comprises:

etching an upper portion of the sacrificial gate electrode layer to form an upper portion of the central region of the sacrificial gate electrode; and

forming a passivation layer that enhances anisotropy of the central region on side walls of the upper portion of the central region.

10. The method of claim 9, wherein the etching the sacrificial gate electrode layer for forming the sacrificial gate electrode comprises:

etching a lower portion of the sacrificial gate electrode layer to form a lower portion of the central region of the sacrificial gate electrode; and

redepositing polymer to form a passivation layer on side walls of the lower portion of the central region and to form the footing regions.

11. The method of claim 8, further comprising:

forming gate spacers on side walls of the sacrificial gate electrode; and

forming fin spacers on side walls of the fin.

12. The method of claim 11, further comprising:

removing at least a portion of the fin between the fin spacers.

13. The method of claim 12, further comprising:

forming a source region and a drain region in the semiconductor structure and on the opposite ends of the sacrificial gate electrode.

14. The method of claim 13, further comprising:

growing stressor material to at least fill spaces between the fin spacers.

15. The method of claim 8, wherein forming the gate electrode to replace the sacrificial gate electrode comprises:

forming a central region and footing regions of the gate electrode, the central region including a gate dielectric, a work function metal layer and a fill metal;

wherein the gate dielectric and the work function metal layer extend to the footing regions of the gate electrode, and the fill metal does not extend to the footing regions of the gate electrode.

16. A method, comprising:

forming a semiconductor structure including a fin protruding from a substrate;

forming a sacrificial gate electrode layer over the semiconductor structure;

etching a first portion of the sacrificial gate electrode layer under a first pressure;

etching a second portion of the sacrificial gate electrode layer lower the first portion under a second pressure different from the first pressure for forming a central region and footing regions of a sacrificial gate electrode, wherein the footing regions are along where the central region is adjacent to the fin.

17. The method of claim 16, wherein the second pressure is higher than the first pressure.

18. The method of claim 17, further comprising:

performing an over etch after the etching of the second portion of the sacrificial gate electrode layer under a third pressure so as to facilitate redeposition of polymer to form a passivation layer on side walls of the central region and to form the footing regions.

19. The method of claim 18, wherein the third pressure is higher than the first pressure and the second pressure.

20. The method of claim 16, further comprising:

forming a gate electrode to replace the sacrificial gate electrode, including forming a central region and footing regions of the gate electrode, the central region including a gate dielectric, a work function metal layer and a fill metal;

wherein the gate dielectric and the work function metal layer extend to the footing regions of the gate electrode, and the fill metal does not extend to the footing regions of the gate electrode.