Forming a sacrificial liner for dual channel devices

• US 10,312,370 B2
• Filed: 07/18/2017
• Issued: 06/04/2019
• Est. Priority Date: 09/26/2016
• Status: Active Grant

• Current Assignee: Tessera LLC (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bu, Huiming, Cheng, Kangguo, Guo, Dechao, Kanakasabapathy, Sivananda K., Xu, Peng
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/652,888
• Publication Number:
  US 20180090599A1
• Time in Patent Office: 686 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.

Claims

1. A method of forming a semiconductor device, comprising:

forming fins on a substrate, the fins having a base portion and a top channel portion which includes a liner;

filling an area around the fins with a flowable dielectric;

annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes sidewalls of the base portion of each fin, such that each fin is narrower in the base portion than in the top channel portion; and

etching away the liner to expose the fins and to open gaps that are below a top surface of the solidified dielectric and between sidewalls of the solidified dielectric and sidewalls of respective adjacent fins.

2. The method of claim 1, further comprising forming a plurality of said fins from two distinct channel materials.

3. The method of claim 2, wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.

4. The method of claim 1, further comprising recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner.

5. The method of claim 1, further comprising:

depositing a gate dielectric layer over the fins and in the gaps; and

depositing a gate over the gate dielectric layer.

6. The method of claim 1, wherein the liner is formed from silicon nitride.

7. The method of claim 1, further comprising forming the fins with an etch that partially etches the substrate.

8. A method of forming a semiconductor device, comprising:

forming fins on a substrate, the fins having a base portion and a top channel portion which includes a liner;

filling an area around the fins with a flowable dielectric;

annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes sidewalls of the base portion of each fin, such that each fin is narrower in the base portion than in the top channel portion; and

recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner.

9. The method of claim 8, further comprising forming a plurality of said fins from two distinct channel materials.

10. The method of claim 9, wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.

11. The method of claim 8, further comprising etching away the liner to expose the fins and gaps at sidewalls of the one or more channel fins.

12. The method of claim 11, further comprising:

depositing a gate dielectric layer over the fins and in the gaps; and

depositing a gate over the gate dielectric layer.

13. The method of claim 8, wherein the liner is formed from silicon nitride.

14. The method of claim 8, further comprising forming the fins with an etch that partially etches the substrate.