Configurable computing array for implementing complex math functions

• US 10,312,917 B2
• Filed: 08/08/2018
• Issued: 06/04/2019
• Est. Priority Date: 03/05/2016
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US16/059,023
• Publication Number:
  US 20180367146A1
• Time in Patent Office: 300 Days
• Field of Search: None
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor

Abstract

To implement a complex math function, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function.

Claims

1. A configurable computing array, comprising:

at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library; and

at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and

, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;

whereby said configurable computing array realizes a complex math function by programming said configurable logic elements and said configurable computing elements, wherein said complex math function is a combination of at least said first and second math functions.

2. The configurable computing array according to claim 1, further comprising at least an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.

3. The configurable computing array according to claim 1, wherein each of said configurable computing elements comprises a re-programmable memory, whereby each of said configurable computing elements can be re-configured to realize a different math function by loading the LUT for said different math function into said re-programmable memory.

4. The configurable computing array according to claim 1, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on a same physical level.

5. The configurable computing array according to claim 1, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on different physical levels.

6. The configurable computing array package according to claim 5, wherein said first and second memories comprise at least a three-dimensional memory (3D-M) array.

7. The configurable computing array according to claim 6, wherein said 3D-M array is a three-dimensional horizontal memory (3D-M_H) array or a three-dimensional vertical memory (3D-M_V) array.

8. The configurable computing array according to claim 5, further comprising a semiconductor substrate with first and second sides, wherein

said configurable logic elements are disposed on said first side;

said configurable computing elements are disposed on said second side;

said configurable logic elements and said configurable computing elements are coupled by a plurality of through-substrate vias through said semiconductor substrate.

9. The configurable computing array according to claim 5, wherein

said configurable logic elements are disposed on at least a configurable logic die;

said configurable computing elements are disposed on at least a configurable computing die;

said configurable logic die and said configurable computing die are located in a same package.

10. The configurable computing array according to claim 1, further comprising at least one multiplier.

11. A configurable computing array, comprising:

at least an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library;

at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library; and

at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and

, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;

whereby said configurable computing array realizes a complex math function by programming said configurable interconnects, said configurable logic elements and said configurable computing elements, wherein said complex math function is a combination of at least said first and second math functions.

12. The configurable computing array according to claim 11, wherein said configurable computing elements comprises a re-programmable memory, whereby each of said configurable computing elements can be re-configured to realize a different math function by loading the LUT for said different math function into said re-programmable memory.

13. The configurable computing array according to claim 11, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on a same physical level.

14. The configurable computing array according to claim 11, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on different physical levels.

15. The configurable computing array according to claim 14, wherein said first and second memories comprise at least a three-dimensional memory (3D-M) array.

16. The configurable computing array according to claim 15, wherein said 3D-M array is a three-dimensional horizontal memory (3D-M_H) array or a three-dimensional vertical memory (3D-M_V) array.

17. The configurable computing array according to claim 15, wherein said 3D-M array at least partially covers said configurable logic element or said configurable interconnect.

18. The configurable computing array according to claim 14, further comprising a semiconductor substrate with first and second sides, wherein

said configurable logic elements are disposed on said first side;

said configurable computing elements are disposed on said second side;

said configurable logic elements and said configurable computing elements are coupled by a plurality of through-substrate vias through said semiconductor substrate.

19. The configurable computing array according to claim 14, wherein

said configurable logic elements are disposed on at least a configurable logic die;

said configurable computing elements are disposed on at least a configurable computing die;

said configurable logic die and said configurable computing die are located in a same package.

20. The configurable computing array according to claim 11, further comprising at least one multiplier.