Scan system interface (SSI) module

• US 10,317,463 B2
• Filed: 10/27/2016
• Issued: 06/11/2019
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sonawane, Milind, Sanghani, Amit, Colburn, Jonathon E., Kumar reddy.S, Rajendra, Nelapatla, Bala Tarun, Chadalavda, Sailendra, Sarangi, Shantanu
• Primary Examiner(s): Vallecillo, Kyle
• Application Number:
  US15/336,747
• Publication Number:
  US 20170115346A1
• Time in Patent Office: 957 Days
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.

Claims

1. A computer system comprising:

a processor; and

memory coupled to said processor and having stored therein instructions that, if executed by said computer system, cause said computer system to execute a method for testing comprising;

sending an instruction to a joint test action group (JTAG) controller to select a first internal test data register of a plurality of data registers; and

programming said first internal test data register to configure mode control access and state control access for a test controller implementing a sequential scan architecture at a system level, wherein said programming said first internal test data register comprises;

programming a mode/state control bit to a second value in said first internal test data register to indicate a state control access during a state write phase;

receiving state control signals received over a JTAG scan-in interface during said state control access, and storing said state control signals in a plurality of dynamic state control registers;

receiving input data over a JTAG scan-in interface and storing said input data in a corresponding register decoded from mode values programmed in a previous mode access, wherein storing of said input data is controlled by said state control signals.

2. The method of claim 1, wherein said programming said first internal test data register comprises:

programming a mode/state control bit to a first value in said first internal test data register to indicate mode control access during a mode write phase; and

programming mode values in said first internal test data register to indicate a test mode and a corresponding register to which input data received over a JTAG scan-in interface is stored in a subsequent state control access.

3. The method of claim 1, further comprising:

resetting said mode/state control bit to a first value to allow writes to said first internal test data register in a subsequent mode write phase.

4. The method of claim 1, further comprising:

disabling production automatic test equipment (ATE) testing.

5. The method of claim 1, further comprising;

generating control signals using a JTAG/IEEE 1500 interface when performing said programming of said first internal test data register.

6. The method of claim 1, further comprising:

alternating between a mode write phase and a state write phase when programming said first internal test data register that is configured receiving mode control signals and state controls signals without accessing an instruction register.

7. The method of claim 1, further comprising:

implementing a dynamic standard test access (DSTA) module to align input data received over said JTAG interface clocked at a first clock with said test controller that is clocked at a slower, second clock.

8. A method for testing, comprising:

sending a single instruction over a joint test action group (JTAG) interface to a JTAG controller to select a first internal test data register of a plurality of data registers;

programming said first internal test data register using said JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level, wherein said programming said first internal test data register comprises;

programming a mode/state control bit to a second value in said first internal test data register to indicate a state control access during a state write phase;

receiving state control signals received over a JTAG scan-in interface during said state control access, and storing said state control signals in a plurality of dynamic state control registers;

receiving input data over a JTAG scan-in interface and storing said input data in a corresponding register decoded from mode values programmed in a previous mode access, wherein storing of said input data is controlled by said state control signals.

9. The method of claim 8, wherein said programming said first internal test data register comprises:

programming a mode/state control bit to a first value in said first internal test data register to indicate mode control access during a mode write phase; and

programming mode values in said first internal test data register to indicate a test mode and a corresponding register to which input data received over a JTAG scan-in interface is stored in a subsequent state control access.

10. The method of claim 8, further comprising:

resetting said mode/state control bit to a first value to allow writes to said first internal test data register in a subsequent mode write phase.

11. A device comprising:

a scan chain selectively configured to test functional components;

a scan chain test controller that controls testing of the functional components; and

an interface module that directs the scan test controller, wherein the interface module includes;

a first port configured to receive a first test control signal to program a first register that coordinates a second first type of testing state and mode information; and

a second port configured to receive a second test control signal to program a second register that coordinates a second type of testing state and mode information, wherein the first test control signal is a higher frequency than the second test control signal.

12. The device of claim 11 wherein the first type of testing is production testing and second type of testing is system testing.

13. The device of claim 12 wherein the second type of testing is on line system testing.

14. The device of claim 11 wherein the second port includes a system scan interface (SSI).

15. The device of claim 14 wherein the system scan interface (SSI) is a joint test action group (JTAG) compatible interface.

16. The device of claim 14 wherein input data is delivered to the scan chain and response data from the scan chain is observed through ports of the SSI JTAG interface.

17. The device of claim 14 wherein the second register is a IEEE 1500 wrapper data register and the system scan interface (SSI) follows an IEEE 1500 based flow.

18. The device of claim 11 wherein the first port includes an ultra fast interface (UFI).