Display device

• US 10,317,763 B2
• Filed: 10/03/2017
• Issued: 06/11/2019
• Est. Priority Date: 11/02/2016
• Status: Active Grant

• Current Assignee: Japan Display Incorporated
• Original Assignee: Japan Display Incorporated
• Inventors: Watakabe, Hajime, Suzumura, Isao, Watanabe, Hirokazu, Hanada, Akihiro
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/723,300
• Publication Number:
  US 20180122835A1
• Time in Patent Office: 616 Days
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/473 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H10K 50/00 : Organic light-emitting devices integrated devices or assemblies of multiple devices H10K59/00, H10K65/00; organic semiconductor lasers H01S5/36
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements

Abstract

A display device comprising: a first TFT using silicon (Si) and a second TFT using oxide semiconductor are formed on a substrate, a distance between the silicon (Si) and the substrate is smaller than a distance between the oxide semiconductor and the substrate, a source/drain electrode of the first TFT connects with the silicon (Si) via a first through hole, a source/drain electrode of the second TFT connects with the oxide semiconductor via a second through hole, metal films are made on the oxide semiconductor sandwiching a channel of the oxide semiconductor in a plan view, the channel has a channel width, an AlO layer is formed on the metal films and the oxide semiconductor, the second source/drain electrode and the metal films are connected via the second through hole formed in the AlO layer.

Claims

1. A display device comprising:

a first TFT using silicon (Si) and a second TFT using oxide semiconductor are formed on a substrate,

a distance between the silicon (Si) and the substrate is smaller than a distance between the oxide semiconductor and the substrate,

a first source/drain electrode of the first TFT connects with the silicon (Si) via a first through hole,

a second source/drain electrode of the second TFT connects with the oxide semiconductor via a second through hole,

metal films are made directly on the oxide semiconductor sandwiching a channel of the oxide semiconductor in a plan view,

an aluminum oxide layer is formed on the metal films and the oxide semiconductor,

the second source/drain electrode and the metal films are connected via the second through hole formed in the aluminum oxide layer.

2. The display device according to claim 1, wherein

the aluminum oxide layer is formed to cover the display area except the area of the first through hole and the area of the second through hole in a plan view.

3. The display device according to claim 1, wherein

the aluminum oxide layer is formed to cover the display area except the area of the silicon (Si) of the first TFT and the area of the second through hole in a plan view.

4. The display device according to claim 1, wherein

the channel has a channel width, and

a width of the channel width direction of the metal film is bigger than the channel width.

5. The display device according to claim 1, wherein

the oxide semiconductor, the metal films and the second through hole overlap in a plan view.

6. The display device according to claim 3, wherein

the oxide semiconductor and the second through hole do not overlap each other in a plan view.

7. The display device according to claim 1, wherein

the channel has a channel width, and

a width of the second through hole in the channel width direction is smaller than a width of the metal films in the channel width direction.

8. The display device according to claim 1, wherein

the first TFT is a top gate type TFT;

a light shielding film of the second TFT is formed simultaneously with the gate electrode of the first TFT.

9. The display device according to claim 1, wherein

the first TFT is a bottom gate type TFT;

a gate electrode of the second TFT is formed simultaneously with the gate electrode of the first TFT.

10. The display device according to claim 1, wherein

the second TFT is formed in a display area.

11. The display device according to claim 1, wherein

the first TFT is formed in a peripheral circuit area that is set at a periphery of the display area.

12. The display device according to claim 1, wherein

the metal films are formed by either one of Ti, Mo, W or Cr or alloys of those metals.

13. The display device according to claim 1, wherein

the display device is a liquid crystal display device.

14. The display device according to claim 1, wherein

the display device is an organic EL display device.