Memory apparatus for executing multiple memory operations by one command and operating method thereof

• US 10,318,208 B2
• Filed: 11/09/2016
• Issued: 06/11/2019
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chang, Chih-Hsiang
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Ho, Aaron D
• Application Number:
  US15/346,732
• Publication Number:
  US 20180005672A1
• Time in Patent Office: 944 Days
• Field of Search: 711105
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A memory apparatus including a memory cell array, a register unit and a command generator is provided. The memory cell array includes a plurality of memory cells. The register unit is configured to record a plurality of user-defined information. The command generator receives a user-defined command and operates at least two memory operations on the memory cell array according to the received user-defined command and the user-defined information. The user-defined information is generated according to the at least two memory operations. Furthermore, an operating method of a memory apparatus is also provided.

Claims

1. A memory apparatus, comprising:

a memory cell array, comprising a plurality of memory cells;

a register unit, configured to record a plurality of pieces of user-defined information, wherein each piece of user-defined information comprises at least two pieces of command information and each piece of command information corresponds to a single memory operation; and

a command generator, coupled to the register unit and the memory cell array,

wherein in response to a single user-defined command received by the command generator from a memory controller, the command generator sequentially executes at least two memory operations on the memory cell array according to the at least two pieces of command of one of the pieces of user-defined which is corresponding to the received user-defined command.

2. The memory apparatus as claimed in claim 1, further comprising:

a detection unit, configured to receive a write signal, and detecting whether the write signal corresponds to at least one of the pieces of user-defined ,

wherein when the write signal corresponds to at least one of the pieces of user-defined information, the corresponding at least one piece of user-defined is recorded in the register unit according to the write signal.

3. The memory apparatus as claimed in claim 1, further comprising:

a signal decoder, configured to receive and decode an external signal, wherein a single memory operation corresponding to the external signal is executed on the memory cell array according to a decoding result of the signal decoder.

4. The memory apparatus as claimed in claim 1, wherein the register unit is a mode register, and at least one of the pieces of user-defined information is written into the mode register in a mode register set state of the memory apparatus.

5. The memory apparatus as claimed in claim 1, wherein each piece of user-defined comprises at least one piece of delay information.

6. The memory apparatus as claimed in claim 5, wherein each piece of user-defined further comprises a piece of loop information,

wherein the command generator repeatedly executes the memory operations on the memory cell array according to the piece of loop information.

7. The memory apparatus as claimed in claim 6, wherein each piece of user-defined further comprises a piece of initial address information and a piece of address increment information,

wherein the command generator sequentially operates at least one memory cell in the memory cell array according to the piece of initial address information, the piece of address increment and the piece of loop information.

8. The memory apparatus as claimed in claim 1, wherein the at least two memory operations corresponding to the at least two pieces of command information in one piece of user-defined comprise a first memory operation and a second memory operation, and the first memory operation is the same to the second memory operation.

9. The memory apparatus as claimed in claim 1, wherein the memory operation is one of no operation, an activate operation, a read operation, a write operation, a precharge operation and a power down operation.

10. The memory apparatus as claimed in claim 1, wherein the user-defined command is generated through at least one hotkey.

11. An operating method of a memory apparatus, adapted to the memory apparatus comprising a memory cell array and a register unit, the operating method of memory apparatus comprising:

writing a plurality of pieces of user-defined information into the register unit, wherein each piece of user-defined comprises at least two pieces of command information and each piece of command corresponds to a single memory operation;

receiving a single user-defined command from a memory controller; and

in response to the user-defined command received, sequentially executing at least two memory operations on the memory cell array according to the at least two pieces of command information of one of the pieces of user-defined information which is corresponding to the received user-defined command.

12. The operating method of the memory apparatus as claimed in claim 11, wherein the step of writing the pieces of user-defined information into the register unit comprises:

receiving a write signal;

detecting whether the write signal corresponds to at least one of the pieces of user-defined information; and

recording the corresponding piece of at least one user-defined information in the register unit according to the write signal when the write signal corresponds to at least one of the pieces of user-defined information.

13. The operating method of the memory apparatus as claimed in claim 11, further comprising:

receiving and decoding an external signal to obtain a decoding result; and

executing a single memory operation corresponding to the external signal on the memory cell array according to the decoding result.

14. The operating method of the memory apparatus as claimed in claim 11, wherein the register unit is a mode register, and at least one of the pieces of user-defined information is written into the mode register in a mode register set state of the memory apparatus.

15. The operating method of the memory apparatus as claimed in claim 11, wherein the step of writing the pieces of user-defined information into the register unit comprises:

for each piece of user-defined information, writing at least one pieces of delay information into the register unit.

16. The operating method of the memory apparatus as claimed in claim 15, wherein the step of writing the pieces of user-defined information into the register unit comprises:

for each piece of user-defined information, writing a piece of loop information into the register unit, wherein the step of sequentially executing the at least two memory operations on the memory cell array according to the at least two pieces of command information of the one of the pieces of user-defined information which is corresponding to the received user-defined command comprises;

repeatedly executing the at least two memory operations on the memory cell array according to the piece of loop information.

17. The operating method of the memory apparatus as claimed in claim 16, wherein the step of writing the pieces of user-defined information into the register unit comprises:

for each piece of user-defined information, writing a piece of initial address information and a piece of address increment into the register unit, wherein the step of sequentially executing the at least two memory operations on the memory cell array according to the at least two pieces of command of the one of the pieces of user-defined information which is corresponding to the received user-defined command comprises;

sequentially executing the at least two memory operations on at least one memory cell in the memory cell array according to the piece of initial address information, the piece of address increment and the piece of loop information.

18. The operating method of the memory apparatus as claimed in claim 11, wherein the step of sequentially executing the at least two memory operations on the memory cell array according to the at least two pieces of command information of the one of the pieces of user-defined which is corresponding to the received user-defined command comprises:

sequentially executing a first memory operation and a second memory operation on the memory cell array according to the at least two pieces of command information of the one of the pieces of user-defined information,

wherein the first memory operation is the same to the second memory operation.

19. The operating method of the memory apparatus as claimed in claim 11, wherein the memory operation is one of no operation, an activate operation, a read operation, a write operation, a precharge operation and a power down operation.

20. The operating method of the memory apparatus as claimed in claim 11, wherein the user-defined command is generated through at least one hotkey.