Thread switching in microprocessor without full save and restore of register file

• US 10,318,302 B2
• Filed: 06/03/2016
• Issued: 06/11/2019
• Est. Priority Date: 06/03/2016
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Tran, Thang
• Primary Examiner(s): Partridge, William B
• Application Number:
  US15/172,864
• Publication Number:
  US 20170351520A1
• Time in Patent Office: 1,103 Days
• Field of Search: 712228, 712217
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register file. The thread switching is achieved without full save and restore of the register file, and only those registers referenced in the memory are saved and restored during thread switching.

Claims

1. A method executed by a microprocessor, comprising:

transmitting a content of a program counter (PC) of a first thread to an instruction fetch unit to start execution of the first thread in the microprocessor;

restoring, upon transmitting the content of the PC of the first thread to the instruction fetch unit, content of one or more registers of the first thread from a memory into a first register file by issuing from the instruction fetch unit a micro-op instruction to read data from the memory, the micro-op instruction issued based on the one or more registers being referenced with regard to the first thread in a scoreboard in the memory;

storing, in the memory, content of one or more other registers of a second register file associated with a second thread by issuing from the instruction fetch unit another micro-op instruction to save data to the memory, the other micro-op instruction issued based on the one or more other registers being referenced with regard to the second thread in the scoreboard or the content of the one or more other registers being modified during execution of the second thread prior to executing the first thread; and

executing instructions of the first thread using the content of the one or more registers restored from the memory.

2. The method of claim 1, wherein restoring the content of the one or more registers of the first thread from the memory further comprises:

determining whether one or more bits in the scoreboard related to one or more source operands of the first thread are set to logical ones or logical zeros;

fetching, based on the one or more bits being determined to be set to logical ones, data for the one or more source operands from the memory into the one or more registers of the first register file; and

clearing the one or more bits in the scoreboard to logical zeroes upon restoring the content of the one or more registers of the first thread from the memory into the first register file.

3. The method of claim 2, wherein fetching the data from the memory comprises:

issuing at least one micro-op instruction to read data for at least one source operand of the one or more source operands from the memory related to an instruction of the first thread; and

replaying the instruction of the first thread from an instruction queue (IQ) using the data for the at least one source operand read from the memory, upon clearing at least one of the one or more bits in the scoreboard.

4. The method of claim 3, wherein issuing the at least one micro-op instruction comprises:

sending, based on the instruction being in a decode unit, the at least one micro-op instruction from the decode unit to a load/store (LS) unit to load the at least one source operand from the memory.

5. The method of claim 3, further comprising:

setting, before replaying the instruction, at least one Reorder Buffer (ROB) valid bit in the scoreboard associated with the at least one source operand of the instruction.

6. The method of claim 1, wherein storing, in the memory, the content of the one or more other registers associated with the second thread further comprises:

determining whether one or more bits in the scoreboard related to one or more source operands of the second thread are set to logical ones or logical zeros;

storing, based on the one or more bits being determined to be set to logical ones, the one or more other registers in the memory;

setting to logical ones one or more other bits in the scoreboard related to the second thread upon storing the content of the one or more other registers in the memory; and

clearing to logical zeroes the one or more bits in the scoreboard upon storing the content of the one or more other registers in the memory.

7. The method of claim 1, wherein storing, in the memory, the content of the one or more other registers associated with the second thread further comprises:

determining whether one or more bits in the scoreboard related to one or more destination operands of the second thread are set to logical ones or logical zeros;

storing, based on the one or more bits being determined to be set to logical ones, the content of the one or more other registers associated with the second thread in the memory; and

setting to logical ones one or more other bits in the scoreboard related to the other thread upon storing the content of the one or more other registers in the memory.

8. The method of claim 1, further comprising:

determining whether one or more bits in the scoreboard related to one or more destination operands of the second thread are set to logical ones or logical zeros;

clearing to logical zeroes one or more bits in the scoreboard related to the thread upon restoring the content of the one or more registers of the thread from the memory into the first register file; and

setting to logical ones one or more other bits in the scoreboard related to content of at least one register of the first register file modified during execution of the first thread.

9. The method of claim 1, wherein storing, in the memory, the content of the one or more other registers associated with the second thread further comprises:

determining that one or more bits in the scoreboard related to the one or more other registers are not set to logical ones; and

storing, based on the one or more bits not set to logical ones, content of at least one of the one or more other registers to the memory, if at least one modify bit in the scoreboard indicating modification of the content of the at least one other register is set to logical one and at least one indication bit in the scoreboard indicating the second thread is set to logical one.

10. The method of claim 1, further comprising:

restoring from the memory content of at least one register of each active thread of a plurality of active threads running in the microprocessor into a register file of that active thread when switching to that active thread, the at least one register being referenced in the scoreboard; and

saving, to the memory, content of at least one other register of the register file when switching from that active thread, the at least one other register is referenced in the scoreboard or the content of the at least one other register modified during execution of that active thread.

11. A microprocessor, comprising:

a first register file associated with a first thread of a plurality of threads;

a program counter (PC) of the first thread;

an instruction fetch unit;

a second register file associated with a second thread of the plurality of threads; and

a scoreboard of a memory, wherein upon the instruction fetch unit receives content of the PC;

the first register file restores from the memory content of one or more registers of the first thread based on a micro-op instruction to read data from the memory issued from the instruction fetch unit based on the one or more registers being referenced with regard to the first thread in the scoreboard, and

the memory stores content of one or more other registers of the second register file based on another micro-op instruction to save data to the memory issued from the instruction fetch unit based on the one or more other registers being referenced with regard to the second thread in the scoreboard or the content of one or more other registers being modified during execution of the second thread prior to executing the first thread.

12. The microprocessor of claim 11, wherein:

the one or more registers are referenced by one or more bits of a set of bits in the scoreboard to the first thread, and

at least one modify bit in the scoreboard indicates modification of the content of the one or more other registers and a thread identifier (ID) bit identifying the second thread.

13. The microprocessor of claim 12, wherein:

the one or more registers of the first register file are loaded with data from the memory for one or more source operands of the first thread, if the one or more bits of the set of bits in the scoreboard related to the one or more source operands of the first thread are set to logical ones, and

the one or more bits are set to logical zeroes when the one or more registers of the first register file comprise the data loaded from the memory.

14. The microprocessor of claim 12, wherein:

the memory is loaded with content of the one or more other registers of the second register file associated with the second thread, when the at least one modify bit indicating modification of one or more source operands of the second thread is set to logical one,

one or more bits of the set of bits in the scoreboard allocated for the second thread are set to logical ones, the one or more bits referencing the one or more other registers, and

the at least one modify bit related to the one or more source operands of the second thread is set to logical zero, when the memory is loaded with the content of the one or more other registers.

15. The microprocessor of claim 12, wherein:

the memory is loaded with content of the one or more other registers of the second register file associated with the second thread, when the at least one modify bit indicating modification of one or more destination operands of the second thread is set to logical one, and

one or more bits of the set of bits in the scoreboard allocated for the second thread are set to logical ones, the one or more bits referencing the one or more other registers.

16. The microprocessor of claim 12, wherein:

the one or more bits of the set of bits in the scoreboard allocated to the first thread are cleared to logical zeroes, when the one or more registers of the first register file associated with the first thread are loaded with data from the memory and if the at least one modify bit indicates that one or more destination operands of the second thread are not modified, and

one or more modify bits of the at least one modify bit and at least one thread ID bit identifying the first thread are set to logical ones, when at least one register of the first register file is modified during execution of the first thread.

17. The microprocessor of claim 12, wherein:

the memory is loaded with content of the one or more other registers of the second register file associated with the second thread, when one or more bits of the set of bits in the scoreboard referencing the one or more other registers are not set to logical ones,

one or more modify bits of the at least one modify bit indicative of modification of the content of the one or more other registers are set to logical ones, and

one or more thread ID bits identifying the second thread are set to logical ones.