System operation queue for transaction

• US 10,318,430 B2
• Filed: 06/26/2015
• Issued: 06/11/2019
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Gschwind, Michael K., Schwarz, Eric M.
• Primary Examiner(s): Geib, Benjamin P
• Assistant Examiner(s): Cromer, Andrew J
• Application Number:
  US14/751,890
• Publication Number:
  US 20160378505A1
• Time in Patent Office: 1,446 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/466 Transaction processing
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Embodiments relate to a system operation queue for a transaction. An aspect includes determining whether a system operation is part of an in-progress transaction of a central processing unit (CPU). Another aspect includes based on determining that the system operation is part of the in-progress transaction, storing the system operation in a system operation queue corresponding to the in-progress transaction. Yet another aspect includes, based on the in-progress transaction ending, processing the system operation in the system operation queue.

Claims

1. A computer program product for implementing a system operation queue for a transaction in a multicore transactional memory system, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising;

determining whether a system operation is part of an in-progress transaction of a central processing unit (CPU), wherein the system operation is an instruction that changes a resource that is shared by multiple CPUs in the multicore transactional memory system;

based on determining that the system operation is part of the in-progress transaction, storing the system operation in a system operation queue corresponding to the in-progress transaction, wherein the system operation queue is stored in a transaction system operation queue logic that is in communication with an issue queue of the CPU;

determining that an end of the in-progress transaction is reached by detecting a transaction end instruction being encountered in the issue queue of the CPU; and

responsive to determining that the end of the in-progress transaction is reached by detecting the transaction end instruction being encountered in the issue queue of the CPU, processing the system operation in the system operation queue, wherein processing the system operation comprises sending a broadcast notification regarding the system operation of the transaction from the CPU to another CPU in the multicore transactional memory system, wherein the broadcast notification comprises a translation lookaside buffer (TLB) invalidate instruction to cause the other CPU to flush an entry in a TLB of the other CPU.

2. The computer program product of claim 1, wherein the system operation comprises an update to a control register.

3. The computer program product of claim 1, further comprising, based on aborting of the in-progress transaction, flushing the system operation queue.

4. The computer program product of claim 1, wherein the system operation queue stores a plurality of system operations corresponding to the in-progress transaction, and further comprising processing each of the plurality of system operations in the system operation queue based on the in-progress transaction ending.

5. The computer program product of claim 1, wherein the determination of whether the system operation is part of an in-progress transaction is made based on the system operation being encountered in the issue queue.

6. The computer program product of claim 5, wherein the transaction system operation queue logic stores a plurality of system operation queues, each of the plurality of system operation queues corresponding to a respective in-progress transaction.

7. The computer program product of claim 6, wherein a number of the plurality of system operation queues is equal to a number of threads supported by the CPU.

8. A multicore transactional memory system comprising:

a memory; and

a processor, communicatively coupled to said memory, the computer system configured to perform a method comprising;

determining whether a system operation is part of an in-progress transaction of a central processing unit (CPU), wherein the system operation is an instruction that changes a resource that is shared by multiple CPUs in the multicore transactional memory system;

based on determining that the system operation is part of the in-progress transaction, storing the system operation in a system operation queue corresponding to the in-progress transaction, wherein the system operation queue is stored in a transaction system operation queue logic that is in communication with an issue queue of the CPU;

determining that an end of the in-progress transaction is reached by detecting a transaction end instruction being encountered in an issue queue of the CPU; and

responsive to determining that the end of the in-progress transaction is reached by detecting the transaction end instruction being encountered in the issue queue of the CPU, processing the system operation in the system operation queue, wherein processing the system operation comprises sending a broadcast notification regarding the system operation of the transaction from the CPU to another CPU in the multicore transactional memory system, wherein the broadcast notification comprises a translation lookaside buffer (TLB) invalidate instruction to cause the other CPU to flush an entry in a TLB of the other CPU.

9. The system of claim 8, wherein the system operation queue stores a plurality of system operations corresponding to the in-progress transaction, and further comprising processing each of the plurality of system operations in the system operation queue based on the in-progress transaction ending.