Efficient context based input/output (I/O) classification

• US 10,318,450 B2
• Filed: 07/01/2016
• Issued: 06/11/2019
• Est. Priority Date: 07/01/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kaminski, Maciej, Wysocki, Piotr, Barczak, Mariusz
• Primary Examiner(s): Abad, Farley
• Application Number:
  US15/201,056
• Publication Number:
  US 20180004690A1
• Time in Patent Office: 1,075 Days
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to define a caching and processing priority policy for one or more input/output (I/O) request class types. The memory controller can monitor one or more I/O contexts of one or more I/O requests. The memory controller can associate the one or more I/O contexts with one or more I/O class types using an I/O context association table. The memory controller can execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types. The apparatus can include an interface to the memory controller.

Claims

1. An apparatus, comprising:

a memory controller with circuitry configured to;

classify one or more input/output (I/O) requests according to I/O classes;

associate one or more I/O contexts extracted from the one or more I/O requests;

to each of the I/O classes;

assign a caching and processing priority policy to each of the I/O classes, wherein the memory controller is configured to use an I/O context association table to associate the one or more I/O contexts to each of the I/O classes in order to update the caching and processing priority policy for one or more subsequent I/O requests;

execute the one or more I/O requests according to the caching and processing priority policy; and

an interface to the memory controller.

2. The apparatus of claim 1, wherein the memory controller is configured to extract the one or more I/O contexts from the one or more I/O requests.

3. The apparatus of claim 1, wherein the memory controller comprises logic further configured to use an offline I/O analytics process, independent from the one or more I/O requests, using shared memory data structures, wherein the shared memory data structures include at least the I/O context association table and an inter process communications channel.

4. The apparatus of claim 3, wherein the memory controller comprises logic further configured to transfer the one or more I/O contexts of the one or more I/O requests that have been processed to an I/O analytics thread.

5. The apparatus of claim 1, wherein the memory controller comprises logic further configured to:

read the one or more I/O contexts of the one or more I/O requests;

analyze the one or more I/O contexts; and

update the I/O context association table; and

update the caching and processing priority policy according to the updated I/O context association table for the one or more subsequent I/O requests.

6. The apparatus of claim 1, wherein the memory controller is configured to classify the one or more I/O requests into the I/O classes based on at least one of data accesses patterns, data types, data storage types associated with the one or more I/O requests, I/O context call instructions, I/O context call parameters, metadata, or one or more read or write operation types.

7. The apparatus of claim 1, further comprising a memory, wherein the memory comprises one or more of a scratchpad memory, an on-chip memory, or an off-chip memory, byte addressable memory, memory devices that use chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level PCM, a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque (STT)-MRAM.

8. The apparatus of claim 1, further comprising one or more of:

a non-volatile memory (NVM), the NVM being communicatively coupled to the memory controller;

a processor communicatively coupled to the memory controller;

a network interface communicatively coupled to a processor;

a display communicatively coupled to a processor;

or

a battery coupled to a processor.

9. A data storage system comprising:

a memory controller comprising logic to;

define a caching and processing priority policy for one or more input/output (I/O) request class types;

monitor one or more I/O contexts of one or more I/O requests;

associate the one or more I/O contexts with one or more I/O class types using an I/O context association table;

extract the caching and processing priority policy from the I/O context association table in order to process the one or more I/O requests;

execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types; and

an interface to the memory controller.

10. The data storage system of claim 9, wherein the memory controller is configured to execute an I/O context extraction call operation to extract an I/O context from the one or more I/O requests upon receiving the one or more I/O requests.

11. The data storage system of claim 10, wherein the memory controller comprises logic further configured to analyze a I/O call context, one or more I/O call parameters, I/O calling thread parameters and metadata of the one or more I/O requests in order to assign the caching and processing priority policy for one or more input/output (I/O) request class types.

12. The data storage system of claim 9, wherein the memory controller is configured to use an offline I/O classification thread in association with one or more I/O requests that are currently being processed.

13. The data storage system of claim 12, wherein the memory controller comprises logic further configured to forward metadata and the one or more I/O contexts of the one or more I/O requests that are currently being processed to the offline I/O classification thread using an inter process communications channel (IPC).

14. The data storage system of claim 9, wherein the memory controller is configured to:

read the one or more I/O contexts and metadata of the one or more I/O requests;

analyze the one or more I/O contexts and metadata of the one or more I/O requests; and

update, at a selected time interval, the I/O context association table according to the one or more I/O contexts and metadata that is analyzed; and

redefine the caching and processing priority policy for executing one or more subsequent I/O requests according to the updated I/O context association table.

15. The data storage system of claim 14, wherein the memory controller comprises logic further configured to extract the redefined caching and processing priority policy from the updated I/O context association table in order to process the one or more subsequent I/O requests.

16. The data storage system of claim 9, wherein the memory controller is configured to analyze the one or more I/O class types according to I/O context and metadata of historically executed I/O requests to define the caching and processing priority policy.

17. The data storage system of claim 9, wherein the memory controller is configured to classify the one or more I/O requests into the one or more I/O class types based on at least one of data accesses patterns, data types, data storage types associated with the one or more I/O requests, I/O context call instructions, I/O context call parameters, metadata, and one or more read or write operation types.

18. The data storage system of claim 9, wherein the memory controller comprises logic further configured to differentiate cold data and hot data, prior to caching the cold data or the hot data, according to the caching and processing priority policy of the one or more I/O class types.

19. The data storage system of claim 9, wherein the memory controller comprises logic further configured to differentiate cold data and hot data, prior to writing the cold data or the hot data to a tiered storage system, according to the caching and processing priority policy of the one or more I/O class types.

20. The data storage system of claim 9, wherein the memory controller comprises logic further configured to differentiate file system metadata write operations and file data write operations according to the caching and processing priority policy of the one or more I/O class types.

21. The data storage system of claim 9, further comprising one or more of:

a non-volatile memory (NVM), the NVM being communicatively coupled to the memory controller;

a processor communicatively coupled to the memory controller;

a network interface communicatively coupled to a processor;

a display communicatively coupled to a processor;

or

a battery coupled to a processor.

22. A method comprising:

under control of at least one processor and memory configured with executable instructions that;

define caching and processing priority policies for one or more input/output (I/O) request class types;

analyze one or more I/O contexts of one or more I/O requests;

associate the one or more I/O contexts with one or more I/O class types using an I/O context association table for executing the one or more I/O requests according to the caching and processing priority policies;

execute the one or more I/O requests according to the caching and processing priority policies of the one or more I/O class types;

update the I/O context association table according to the one or more I/O contexts and metadata of the one or more I/O requests that have been processed in order to update the caching and processing priority policies for executing one or more subsequent I/O requests.

23. The method of claim 22, wherein the executable instructions further extract one or more I/O contexts of one or more I/O requests upon receiving one or more I/O requests.

24. The method of claim 22, wherein the executable instructions further use an offline I/O classification thread in association with one or more I/O requests that are currently being processed.

25. The method of claim 24, wherein the executable instructions further forward metadata and the one or more I/O contexts of the one or more I/O requests that are currently being processed to the offline I/O classification thread using an inter process communications channel (IPC).

26. The method of claim 22, wherein the executable instructions further:

read the one or more I/O contexts and metadata of the one or more I/O requests;

analyze the one or more I/O contexts and metadata of the one or more I/O requests;

update, at a selected time interval, the I/O context association table according to the one or more I/O contexts and metadata that is analyzed; and

redefine the caching and processing priority policy for executing one or more subsequent I/O requests according to the updated I/O context association table.

27. The method of claim 22, wherein the executable instructions further extract the caching and processing priority policy from the I/O context association table in order to process the one or more I/O requests.

28. The method of claim 22, wherein the executable instructions further classify the one or more I/O requests into the one or more I/O class types based on at least one of data accesses patterns, data types, data storage types associated with the one or more I/O requests, I/O context call instructions, I/O context call parameters, metadata, and one or more read or write operation types.