Adjustable current selectors

• US 10,319,424 B1
• Filed: 01/08/2018
• Issued: 06/11/2019
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Kim, Kuk-Hwan, Sharma, Gian, Levi, Amitay
• Primary Examiner(s): Nguyen, Vanthu T
• Application Number:
  US15/865,125
• Time in Patent Office: 519 Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/165 Auxiliary circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a magnetic memory component; and (2) a current selector component coupled to the magnetic memory component, the current selector component including: (a) a first transistor having a first gate with a corresponding first threshold voltage; and (b) a second transistor having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage; where the second transistor is coupled in parallel with the first transistor.

Claims

1. A memory device, comprising:

a magnetic memory component;

a current selector component coupled to the magnetic memory component, the current selector component comprising;

a first transistor having a first gate with a corresponding first threshold voltage, wherein the first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor; and

a second transistor coupled in parallel with the first transistor, the second transistor having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage; and

control circuitry configured to;

determine a bit error rate of the magnetic memory component; and

adjust a charge stored in the charge storage layer based on the determined bit error rate.

2. The memory device of claim 1, further comprising a source line;

and

wherein the magnetic memory component is coupled to the source line via the current selector component.

3. The memory device of claim 1, further comprising a first wordline and a second wordline;

and

wherein the first gate is coupled to the first wordline and the second gate is coupled to the second wordline.

4. The memory device of claim 1, wherein the current selector component is configured to selectively supply a plurality of currents to the magnetic memory component.

5. The memory device of claim 4, wherein the plurality of currents corresponds to a plurality of current thresholds for reading and writing to the magnetic memory component.

6. The memory device of claim 4, wherein the control circuitry is configured to select a particular current of the plurality of currents based on a temperature of the magnetic memory component.

7. The memory device of claim 4, wherein the control circuitry is configured to select a particular current of the plurality of currents based on a desired error rate for the magnetic memory component.

8. The memory device of claim 1, wherein the charge storage layer is a floating gate or charge trap.

9. The memory device of claim 1, wherein the control circuitry is configured to repeat the determining and the adjusting until the determined bit error rate is within a desired bit error range.

10. The memory device of claim 1, further comprising a bitline;

and

wherein the current selector component is coupled to the bitline via the magnetic memory component.

11. The memory device of claim 10, wherein the current selector component is further coupled to the bitline via bypass circuitry configured to bypass the magnetic memory component.

12. The memory device of claim 10, further comprising a program line;

and

wherein the current selector component is coupled to the program line via bypass circuitry configured to selectively couple the current selector component to the program line and selectively decouple the magnetic memory component from the current selector component.