Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits

• US 10,319,425 B1
• Filed: 03/29/2018
• Issued: 06/11/2019
• Est. Priority Date: 03/29/2018
• Status: Active Grant

• Current Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.), University-Industry Foundation Yonsei University
• Original Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.), University-Industry Foundation Yonsei University
• Inventors: Jung, Seong-Ook, Song, Byungkyu, Kim, Sungryul, Kim, Jung Pill, Kang, Seung Hyuk
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US15/939,514
• Time in Patent Office: 439 Days
• Field of Search: 365154, 365205
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

Claims

1. A sensing circuit, comprising:

a differential amplifier, comprising;

an output node configured to receive an output voltage;

a complement output node configured to receive a complement output voltage;

a differential transistor comprising a first gate, a first node, and a second node coupled to a ground node;

a complement differential transistor comprising a second gate, a third node, and a fourth node coupled to the ground node;

a pre-charge control circuit coupled between the first gate and the complement output node, the pre-charge control circuit configured to be activated to couple the first gate to the output node;

a complement pre-charge control circuit coupled between the second gate and the output node, the complement pre-charge control circuit configured to be activated to couple the second gate to the complement output node;

a ground control circuit coupled between the ground node and a capacitor node;

a complement ground control circuit coupled between the ground node and a complement capacitor node;

a capacitor circuit coupled between the first gate and the capacitor node; and

a complement capacitor circuit coupled between the second gate and the complement capacitor node;

a non-volatile (NV) memory circuit coupled between the complement output node and a supply node, the NV memory circuit configured to store a memory state;

a complement NV memory circuit coupled between the output node and the supply node, the complement NV memory circuit configured to store a complement memory state complementary to the memory state; and

a differential amplifier control circuit coupled to a supply voltage node configured to receive a supply voltage and the supply node.

2. The sensing circuit of claim 1, further comprising:

a second pre-charge control circuit coupled between the capacitor node and the output node; and

a second complement pre-charge control circuit coupled between the complement capacitor node and the complement output node.

3. The sensing circuit of claim 2, wherein:

the second pre-charge control circuit comprises a first pass gate comprising a gate, a first node coupled to the capacitor node, and a second node coupled to the output node; and

the second complement pre-charge control circuit comprises a second pass gate comprising a gate, a first node coupled to the complement capacitor node, and a second node coupled to the complement output node.

4. The sensing circuit of claim 1, wherein:

the pre-charge control circuit comprises a pass gate comprising a gate, a first node coupled to the output node, and a second node coupled to the differential transistor; and

the complement pre-charge control circuit comprises a pass gate comprising a gate, a first node coupled to the complement output node, and a second node coupled to the complement differential transistor.

5. The sensing circuit of claim 1, wherein:

the ground control circuit comprises a transistor comprising a gate, a first node coupled to the capacitor node, and a second node coupled to the ground node; and

the complement ground control circuit comprises a transistor comprising a gate, a first node coupled to the complement capacitor node, and a second node coupled to the ground node.

6. The sensing circuit of claim 1, wherein:

the NV memory circuit comprises a magnetic tunnel junction (MTJ); and

the complement NV memory circuit comprises a complement MTJ.

7. The sensing circuit of claim 1, wherein:

the differential transistor comprises an N-type metal-oxide semiconductor (MOS) (NMOS) transistor; and

the complement differential transistor comprises an NMOS transistor.

8. The sensing circuit of claim 1, wherein:

the differential amplifier control circuit is coupled to a first pre-charge input;

the pre-charge control circuit is coupled to the first pre-charge input;

the complement pre-charge control circuit is coupled to the first pre-charge input;

the ground control circuit is coupled to the first pre-charge input; and

the complement ground control circuit is coupled to the first pre-charge input; and

in response to a first pre-charge input signal on the first pre-charge input indicating a first pre-charge operational phase;

the differential amplifier control circuit is configured to couple the supply voltage to the NV memory circuit and the complement NV memory circuit;

the ground control circuit is configured to couple the capacitor node to the ground node;

the complement ground control circuit is configured to couple the complement capacitor node to the ground node;

the pre-charge control circuit is configured to couple the NV memory circuit to the first gate of the differential transistor to pre-charge the first gate of the differential transistor to a first pre-charge voltage based on the supply voltage, and store the first pre-charge voltage in the capacitor circuit; and

the complement pre-charge control circuit is configured to couple the complement NV memory circuit to the second gate of the complement differential transistor to pre-charge the second gate of the complement differential transistor to a first complement pre-charge voltage based on the supply voltage, and store the first complement pre-charge voltage in the complement capacitor circuit.

9. The sensing circuit of claim 8, wherein:

the pre-charge control circuit is coupled to an offset-cancellation input;

the complement pre-charge control circuit is coupled to the offset-cancellation input;

the ground control circuit is coupled to the offset-cancellation input; and

the complement ground control circuit is coupled to the offset-cancellation input; and

in response to an offset-cancellation input signal on the offset-cancellation input indicating an offset-cancellation operational phase;

the ground control circuit is configured to couple the capacitor node to the ground node;

the complement ground control circuit is configured to couple the complement capacitor node to the ground node;

the pre-charge control circuit is configured to couple the first gate of the differential transistor to the first node of the differential transistor to discharge the capacitor circuit on the first gate of the differential transistor to a threshold voltage of the differential transistor; and

the complement pre-charge control circuit is configured to couple the second gate of the complement differential transistor to the third node of the complement differential transistor to discharge the first complement pre-charge voltage from the complement capacitor circuit on the first gate of the differential transistor to a complement threshold voltage of the complement differential transistor;

the threshold voltage on the first gate of the differential transistor and the complement threshold voltage of the second gate of the complement differential transistor configured to substantially cancel an offset voltage of the differential amplifier control circuit.

10. The sensing circuit of claim 9, wherein in response to the offset-cancellation input signal indicating the offset-cancellation operational phase, the differential amplifier control circuit is configured to decouple the supply voltage from the NV memory circuit and the complement NV memory circuit.

11. The sensing circuit of claim 9, wherein:

the ground control circuit is coupled to a second pre-charge input; and

the complement ground control circuit is coupled to the second pre-charge input; and

in response to a second pre-charge input signal on the second pre-charge input indicating a second pre-charge operational phase;

the ground control circuit is configured to couple the capacitor node to the ground node to pre-charge the output node to a ground voltage on the ground node; and

the complement ground control circuit is configured to couple the complement capacitor node to the ground node to pre-charge the complement output node to the ground voltage on the ground node.

12. The sensing circuit of claim 11, wherein in response to the second pre-charge input signal indicating the second pre-charge operational phase:

the differential amplifier control circuit is configured to decouple the supply voltage from the NV memory circuit and the complement NV memory circuit;

the pre-charge control circuit is configured to decouple the NV memory circuit from the first gate of the differential transistor; and

the complement pre-charge control circuit is configured to decouple the complement NV memory circuit from the second gate of the complement differential transistor.

13. The sensing circuit of claim 11, wherein:

the differential amplifier control circuit is coupled to a comparison input; and

in response to a comparison input signal on the comparison input indicating a comparison operational phase;

the differential amplifier control circuit is configured to couple the supply voltage to the NV memory circuit and the complement NV memory circuit;

the sensing circuit is configured to apply a voltage on the first node of the differential transistor to the second gate of the complement differential transistor; and

the sensing circuit is configured to apply is configured a complement voltage on the third node of the complement differential transistor to the first gate of the differential transistor;

wherein;

the output voltage on the output node represents a difference in resistance between the NV memory circuit and the complement NV memory circuit; and

the complement output voltage on the complement output node represents a difference in resistance between the complement NV memory circuit and the NV memory circuit.

14. The sensing circuit of claim 13, wherein:

the pre-charge control circuit is coupled to the comparison input;

the complement pre-charge control circuit is coupled to the comparison input; and

in response to the comparison input signal on the comparison input indicating the comparison operational phase;

the pre-charge control circuit is configured to decouple the first gate of the differential transistor from the NV memory circuit; and

the complement pre-charge control circuit is configured to decouple the second gate of the complement differential transistor from the complement NV memory circuit.

15. The sensing circuit of claim 1 integrated into an integrated circuit (IC).

16. The sensing circuit of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a global positioning system (GPS) device;

a mobile phone;

a cellular phone;

a smart phone;

a session initiation protocol (SIP) phone;

a tablet;

a phablet;

a server;

a computer;

a portable computer;

a mobile computing device;

a wearable computing device;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player;

a portable digital video player;

an automobile;

a vehicle component;

avionics systems;

a drone; and

a multicopter.

17. A sensing circuit, comprising:

a means for pre-charging a gate of a differential transistor to a pre-charge voltage based on a supply voltage coupled to a supply node, the differential transistor coupled between a non-volatile (NV) memory circuit and a ground node, and a means for pre-charging a gate of a complement differential transistor to a complement pre-charge voltage based on the supply voltage coupled to the supply node, the complement differential transistor coupled between a complement NV memory circuit and the ground node;

a means for pre-charging a capacitor circuit coupled between the gate of the differential transistor and the ground node based on the pre-charge voltage applied to the gate of the differential transistor, and a means for pre-charging a complement capacitor circuit coupled between the gate of the complement differential transistor and the ground node based on the complement pre-charge voltage applied to the gate of the complement differential transistor;

a means for discharging the capacitor circuit onto the gate of the differential transistor to couple the NV memory circuit to the ground node to discharge the pre-charge voltage on the gate of the differential transistor to a threshold voltage of the differential transistor, and a means for discharging the complement capacitor circuit onto the gate of the complement differential transistor to couple the complement NV memory circuit to the ground node to discharge the complement pre-charge voltage on the gate of the complement differential transistor to a complement threshold voltage of the complement differential transistor, to substantially cancel offset voltages of the differential transistor and the complement differential transistor;

a means for pre-charging an output node to a ground voltage on the ground node coupled to the complement NV memory circuit, and a means for pre-charging a complement output node to the ground voltage on the ground node coupled to the NV memory circuit; and

a means for applying the supply voltage to the NV memory circuit to generate a read current through the NV memory circuit based on a resistance of the NV memory circuit to generate a complement output voltage on the complement output node to activate the complement differential transistor, and a means for applying the supply voltage to the complement NV memory circuit to generate a complement read current through the complement NV memory circuit based on a resistance of the complement NV memory circuit to generate the output voltage on the output node to activate the differential transistor, such that the output voltage on the output node represents a difference in resistance between the NV memory circuit and the complement NV memory circuit, wherein the complement output voltage on the complement output node represents a difference in resistance between the complement NV memory circuit and the NV memory circuit.

18. A method of sensing a differential voltage based on a difference in stored memory states in a non-volatile (NV) memory circuit and a complement NV memory circuit, comprising:

pre-charging a first gate of a differential transistor to a pre-charge voltage based on a supply voltage coupled to a supply node, the differential transistor coupled between an NV memory circuit and a ground node, and pre-charging a second gate of a complement differential transistor to a complement pre-charge voltage based on the supply voltage coupled to the supply node, the complement differential transistor coupled between a complement NV memory circuit and the ground node;

pre-charging a capacitor circuit coupled between the gate of the differential transistor and the ground node based on the pre-charge voltage applied to the gate of the differential transistor, and pre-charging a complement capacitor circuit coupled between the gate of the complement differential transistor and the ground node based on the complement pre-charge voltage applied to the gate of the complement differential transistor;

discharging the capacitor circuit onto the gate of the differential transistor to couple the NV memory circuit to the ground node to discharge the pre-charge voltage on the gate of the differential transistor to a threshold voltage of the differential transistor, and discharging the complement capacitor circuit onto the gate of the complement differential transistor to couple the complement NV memory circuit to the ground node to discharge the complement pre-charge voltage on the gate of the complement differential transistor to a complement threshold voltage of the complement differential transistor, to substantially cancel offset voltages of the differential transistor and the complement differential transistor;

pre-charging an output node to a ground voltage on the ground node coupled to the complement NV memory circuit, and pre-charging a complement output node to the ground voltage on the ground node coupled to the NV memory circuit; and

applying the supply voltage to the NV memory circuit to generate a read current to flow through the NV memory circuit based on a resistance of the NV memory circuit to generate a complement output voltage on the complement output node to activate the complement differential transistor, and applying the supply voltage to the complement NV memory circuit to generate a complement read current to flow through the complement NV memory circuit based on a resistance of the complement NV memory circuit to generate an output voltage on the output node to activate the differential transistor, such that the output voltage on the output node represents a difference in resistance between the NV memory circuit and the complement NV memory circuit, the complement output voltage on the complement output node represents a difference in resistance between the complement NV memory circuit and the NV memory circuit.

19. A non-volatile (NV) memory circuit, comprising:

a latch circuit, comprising;

a latch input configured to receive an input data signal; and

a latch output;

the latch circuit configured to latch input data based on the received latch input data signal and generate an output data signal on the latch input based on the latch input data;

a sensing circuit, comprising;

a differential amplifier, comprising;

an output node configured to receive an output voltage;

a complement output node configured to receive a complement output voltage;

a differential transistor comprising a first gate, a first node, and a second node coupled to a ground node;

a complement differential transistor comprising a second gate, a third node, and a fourth node coupled to the ground node;

a pre-charge control circuit coupled between the first gate and the output node, the first pre-charge control circuit configured to be activated to couple the first gate to the output node;

a complement pre-charge control circuit coupled between the second gate and the complement output node, the complement pre-charge control circuit configured to be activated to couple the second gate to the complement output node;

a ground control circuit coupled between the ground node and a capacitor node;

a complement ground control circuit coupled between the ground node and a complement capacitor node;

a capacitor circuit coupled between the first gate and the capacitor node; and

a complement capacitor circuit coupled between the second gate and the complement capacitor node;

the NV memory circuit coupled between the complement output node and a supply node, the NV memory circuit configured to store a memory state;

a complement NV memory circuit coupled between the output node and the supply node, the complement NV memory circuit configured to store a complement memory state complementary to the memory state; and

a differential amplifier control circuit coupled to a supply voltage node configured to receive a supply voltage and the supply node; and

a write circuit coupled to the latch output, the output node, and the complement output node, configured to receive the latch input data, the write circuit configured to write a write output signal based on the output data signal to the output node to be stored in the NV memory circuit, and write a complement write output signal, complementary to the write output signal, based on the output data signal to the complement output node to be stored in the complement NV memory circuit.

20. The NV memory circuit of claim 19, wherein the latch circuit does not share any transistors with the sensing circuit.

21. The NV memory circuit of claim 19, wherein the write circuit further comprises a write enable input;

and

in response to a write enable signal on the write enable input indicating a write operational phase, the write circuit is configured to assert the latch output to the output node to cause a current to flow through the NV memory circuit and the complement NV memory circuit to program the NV memory circuit to the memory state based on the latch output and program the complement NV memory circuit to the complement memory state based on the latch output.

22. The NV memory circuit of claim 21, wherein the NV memory circuit comprises a magnetic tunnel junction (MTJ) and the complement NV memory circuit comprises a complement MTJ.

23. The NV memory circuit of claim 22, wherein, in response to the write enable signal on the write enable input indicating the write operational phase and the latch output being a logical ‘

0’

memory state, the write circuit is configured to assert the latch output to the output node to cause a current to flow from the MTJ to the complement MTJ to program the MTJ to an anti-parallel (AP) magnetic orientation and program the complement MTJ to a parallel (P) magnetic orientation.

24. The NV memory circuit of claim 22, wherein in response to the write enable signal on the write enable input indicating the write operational phase and the latch output being a logical ‘

1’

memory state, the write circuit is configured to assert the latch output to the output node to cause a current to flow from the complement MTJ to the MTJ to program the complement MTJ to an anti-parallel (AP) magnetic orientation and program the MTJ to a parallel (P) magnetic orientation.

25. The NV memory circuit of claim 19, wherein the write circuit further comprises:

a write driver circuit coupled to the output node; and

the write driver circuit configured to assert the write output signal based on the output data signal to the output node and assert the complement write output signal based on the complement output data signal to the complement output node.

26. The NV memory circuit of claim 19, wherein the latch circuit comprises a flip-flop.