Semiconductor device
First Claim
1. A semiconductor device comprising:
- a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and
a peripheral circuit region disposed outside of the memory cell region, and including low voltage transistors and high voltage transistors,wherein the low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon, wherein the low voltage transistors have a channel length shorter than a channel length of the high voltage transistors.
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Accused Products
Abstract
A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
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Citations
19 Claims
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1. A semiconductor device comprising:
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a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and a peripheral circuit region disposed outside of the memory cell region, and including low voltage transistors and high voltage transistors, wherein the low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon, wherein the low voltage transistors have a channel length shorter than a channel length of the high voltage transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and a peripheral circuit region disposed outside of the memory cell region, and including first transistors generating an electrical signal required for communications between the memory cells and an external host and second transistors generating an electrical signal required for operations of the memory cells and, wherein the first transistors include a first gate dielectric layer and first gate electrode layer including a first metal layer and a second metal layer, and the second transistors include a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer. - View Dependent Claims (16, 17)
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18. A semiconductor device comprising:
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a memory cell region including memory cells including a charge storage layer; and a peripheral circuit region disposed outside of the memory cell region, and including first transistors including a first gate dielectric layer including a high-k material and a first gate electrode layer, and second transistors including a second gate dielectric layer including silicon dioxide (SiO2) and a second gate electrode layer including polysilicon, wherein the first transistors comprise n-type transistors and p-type transistors, the first gate electrode layer of the n-type transistors comprises a first metal layer, and the first gate electrode layer of the p-type transistors comprises a second metal layer, wherein the first metal layer is different from the second metal layer. - View Dependent Claims (19)
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Specification