Resistive processing unit weight reading via collection of differential current from first and second memory elements

• US 10,319,439 B1
• Filed: 05/15/2018
• Issued: 06/11/2019
• Est. Priority Date: 05/15/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Yulong, Solomon, Paul M.
• Primary Examiner(s): Dinh, Son T
• Application Number:
  US15/979,759
• Time in Patent Office: 392 Days
• Field of Search: 36518503, 365148
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/005 Read using potential difference applied between cell electrodes
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A resistive processing unit includes a first analog memory element, a second analog memory element connected in series with the first analog memory element, and a control circuit coupled to the first analog memory element and the second analog memory element. The control circuit is configured to read a synaptic weight value of the resistive processing unit by collecting a differential current from the first analog memory element and the second analog memory element on at least one of a read column line and a read row line coupled to a terminal coupling the first analog memory element and the second analog memory element.

Claims

1. A resistive processing unit, comprising:

a first analog memory element;

a second analog memory element connected in series with the first analog memory element; and

a control circuit coupled to the first analog memory element and the second analog memory element, the control circuit configured to read a synaptic weight value of the resistive processing unit by collecting a differential current from the first analog memory element and the second analog memory element on at least one of a read column line and a read row line coupled to a terminal coupling the first analog memory element and the second analog memory element.

2. The resistive processing unit of claim 1, wherein the first analog memory element and the second analog memory element comprise resistive random-access memory (RRAM) devices.

3. The resistive processing unit of claim 1, wherein the control circuit is configured, in a forward pass operation, to measure the differential current on the read column line.

4. The resistive processing unit of claim 1, wherein the control circuit is configured, in a backward pass operation, to measure the differential current on the read row line.

5. The resistive processing unit of claim 1, wherein the differential current is determined according to:

6. The resistive processing unit of claim 5, wherein the sign of (g1-g2) corresponds to the sign of the synaptic weight of the resistive processing unit.

7. The resistive processing unit of claim 1, wherein the control circuit comprises:

a first pass transistor comprising a gate, a first source/drain terminal and a second source/drain terminal; and

a second pass transistor comprising a gate, a first source/drain terminal and a second source/drain terminal;

wherein the gate of the first pass transistor is coupled to a first control line and the gate of the second pass transistor is coupled to a second control line;

wherein the first source/drain terminal of the first pass transistor is coupled to the read row line and the second source/drain terminal of the second pass transistor is coupled to the read column line;

wherein the second source/drain terminal of the first pass transistor is coupled to the first source/drain terminal of the second pass transistor and the terminal coupling the first and second analog memory elements.

8. The resistive processing unit of claim 7, wherein the control circuit is configured in a forward pass operation:

to apply a voltage difference across the first and second analog memory elements;

to apply a first fixed voltage to the first control line to turn off the first pass transistor;

to apply a read pulse voltage to the second control line to turn on the second pass transistor when the read pulse is at a given voltage; and

to read the differential current on the read column line when the read pulse is at the given voltage.

9. The resistive processing unit of claim 7, wherein the control circuit is configured in a backward pass operation:

to apply a voltage difference across the first and second analog memory elements;

to apply a first fixed voltage to the second control line to turn off the second pass transistor;

to apply a read pulse voltage to the first control line to turn on the first pass transistor when the read pulse is at a given voltage; and

to read the differential current on the read row line when the read pulse is at the given voltage.

10. The resistive processing unit of claim 7, wherein the control circuit is configured in a weight update operation:

to apply synchronized pulses to a first terminal of the first analog memory element and to a second terminal of the second analog memory element, a second terminal of the first analog memory element being coupled to a first terminal of the second analog memory element;

to apply a first fixed voltage to the first control line to at least partially turn on the first pass transistor;

to apply a second fixed voltage to the second control line to turn off the second pass transistor; and

to apply a pulse voltage to the read row line;

wherein the weight update is a positive weight update that increases a conductance of the first analog memory element and decreases a conductance of the second analog memory element when the pulse voltage applied to the read row line is negative and coincident with positive synchronized pulses applied to the first terminal and the second terminal; and

wherein the weight update is a negative weight update that decreases the conductance of the first analog memory element and increases the conductance of the second analog memory element when the pulse voltage applied to the read row line is positive and coincident with negative synchronized pulses applied to the first terminal and the second terminal.

11. The resistive processing unit of claim 7, wherein the control circuit further comprises an AND logic gate coupled to the first control line, and wherein the control circuit is configured in a weight update operation:

to apply a first fixed voltage to a first terminal of the first analog memory element and to a second terminal of the second analog memory element, a second terminal of the first analog memory element being coupled to a first terminal of the second analog memory element;

to apply pulse voltages to a first terminal and a second terminal of the AND logic gate coupled to the first control line to at least partially turn on the first pass transistor when the pulse voltages applied to the first terminal and the second terminal of the AND logic gate are coincident;

to apply a second fixed voltage to the second control line to turn off the second pass transistor; and

to apply a third fixed voltage to the read row line;

wherein the weight update is a positive weight update that increases a conductance of the first analog memory element and decreases a conductance of the second analog memory element when the first fixed voltage is a first value, the third fixed voltage is a second value lower than the first value, and the first pass transistor is at least partially turned on; and

wherein the weight update is a negative weight update that decreases the conductance of the first analog memory element and increases the conductance of the second analog memory element when the first fixed voltage is the second value, the third fixed voltage is the first value, and the first pass transistor is at least partially turned on.

12. The resistive processing unit of claim 1, wherein the control circuit comprises:

a first pass transistor comprising a gate, a first source/drain terminal and a second source/drain terminal; and

a second pass transistor comprising a gate, a first source/drain terminal and a second source/drain terminal;

wherein the gate of the first pass transistor is coupled to the read column line and the gate of the second pass transistor is coupled to the read row line;

wherein the first source/drain terminal of the first pass transistor is coupled to the read row line and the second source/drain terminal of the second pass transistor is coupled to the read column line;

wherein the second source/drain terminal of the first pass transistor is coupled to the first source/drain terminal of the second pass transistor and the terminal coupling the first and second analog memory elements.

13. The resistive processing unit of claim 12, wherein the control circuit is configured:

in a forward pass operation;

to apply a voltage difference across the first and second analog memory elements;

to apply a first fixed voltage to the read column line to turn off the first pass transistor;

to apply a read pulse voltage to the read row line; and

to read the differential current on the read column line when the second pass transistor is turned on by the read pulse voltage;

in a backward pass operation;

to apply the voltage difference across the first and second analog memory elements;

to apply the first fixed voltage to the read row line to turn off the second pass transistor;

to apply the read pulse voltage to the read column line; and

to read the differential current on the read row line when the first pass transistor is turned on by the read pulse voltage.

14. The resistive processing unit of claim 12, wherein the control circuit is configured in a weight update operation:

to apply a synchronized first pulse voltage to a first terminal of the first analog memory element and to a second terminal of the second analog memory element, a second terminal of the first analog memory element being coupled to a first terminal of the second analog memory element;

to apply a second pulse voltage to the read row line; and

to apply a fixed voltage to the read column line that turns off the first pass transistor;

wherein the weight update occurs when the first synchronized pulse voltage is coincident with the second pulse voltage and the second pulse voltage turns on the second pass transistor.

15. The resistive processing unit of claim 1, wherein the control circuit comprises:

a first pass transistor comprising a gate, a first source/drain terminal and a second source/drain terminal;

a second pass transistor comprising a gate, a first source/drain terminal and a second source/drain terminal; and

an analog selector;

wherein the gate of the first pass transistor is coupled to the read column line and the gate of the second pass transistor is coupled to the read row line;

wherein the first source/drain terminal of the first pass transistor is coupled to the read row line and the second source/drain terminal of the second pass transistor is coupled to the read column line;

wherein the second source/drain terminal of the first pass transistor is coupled, via the analog selector, to the first source/drain terminal of the second pass transistor and the terminal coupling the first and second analog memory elements.

16. The resistive processing unit of claim 15, wherein the control circuit further comprises a NAND logic gate coupled to a third transistor, the NAND logic gate comprising a first terminal coupled to the read column line and a second terminal coupled to the read row line, the third transistor comprising a gate coupled to an output of the NAND logic gate, a first source/drain terminal coupled to the terminal coupling the first and second analog memory elements, and a second source/drain terminal coupled to a supply voltage.

17. The resistive processing unit of claim 16, wherein the analog selector comprises a read enable terminal coupled to gates of a fourth transistor and a fifth transistor, a first source/drain terminal of the fourth transistor being coupled to the second source/drain terminal of the first pass transistor, a first source/drain terminal of the fifth transistor being coupled to the first source/drain terminal of the first pass transistor, and a second source/drain terminal of the fourth transistor being coupled to a second source/drain terminal of the fifth transistor and to the terminal coupling the first and second analog memory elements.

18. An integrated circuit comprising:

an array of two or more resistive processing units;

wherein a given one of the resistive processing units comprises;

a first analog memory element;

a second analog memory element connected in series with the first analog memory element; and

a control circuit coupled to the first analog memory element and the second analog memory element, the control circuit configured to read out a synaptic weight value of the resistive processing unit by collecting a differential current from the first analog memory element and the second analog memory element.

19. A method for differential weight reading of a resistive processing unit, comprising:

applying a voltage difference across a first analog memory element and a second analog memory element of the resistive processing unit utilizing a control circuit, the first analog memory element being connected in series with the second analog memory element;

applying one or more read pulse voltages utilizing the control circuit; and

reading a synaptic weight value of the resistive processing unit by collecting a differential current from the first analog memory element and the second analog memory element on at least one of a read column line and a read row line coupled to a terminal between the first analog memory element and the second analog memory element.

20. The method of claim 19, further comprising performing a weight update to simultaneously update a conductance of the first analog memory element and a conductance of the second analog memory element.