Low-overhead mechanism to detect address faults in ECC-protected memories
First Claim
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1. An apparatus comprising:
- a memory array;
an error correction code (ECC) encoder circuit for the memory array to encode, during a write operation of a data value into the memory array, an ECC value based on the data value and a write address value for the data value;
an ECC decoder circuit for the memory array to receive, during a read operation of the data value, a read ECC value and a read data value from the memory array and to receive a read address value for the data value;
wherein the apparatus is to detect and correct an error in the write or read address values based on the read ECC value, the read address value, and the read data value;
wherein the apparatus is to roll back stored data values of all or a portion of the memory array to an earlier state upon detecting the error in the read or write address values.
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Accused Products
Abstract
Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.
8 Citations
19 Claims
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1. An apparatus comprising:
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a memory array; an error correction code (ECC) encoder circuit for the memory array to encode, during a write operation of a data value into the memory array, an ECC value based on the data value and a write address value for the data value; an ECC decoder circuit for the memory array to receive, during a read operation of the data value, a read ECC value and a read data value from the memory array and to receive a read address value for the data value; wherein the apparatus is to detect and correct an error in the write or read address values based on the read ECC value, the read address value, and the read data value; wherein the apparatus is to roll back stored data values of all or a portion of the memory array to an earlier state upon detecting the error in the read or write address values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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receiving a command to read from a memory array at an address value; reading a data value and an error correction code (ECC) value from the memory array based on the address value, wherein, during a previous write of the data value, the ECC value was generated based on the data value and its write address value; performing a decoding operation using the address value, the data value and the ECC value; identifying one or more errors in the address value or write address value based on the decoding operation; and
,rolling back stored data values of all or a portion of the memory array to an earlier state upon detecting the one or more errors. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A computing system comprising:
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one or more processors for processing of data; a memory apparatus for storage of data, the memory apparatus including a memory array; a wireless transmitter or receiver and one or more antennae for transmission or reception of data; and
,the computing system further comprising error correction code (ECC) logic, including; an ECC encoder to encode an ECC value based on a data value and a respective write address value for the writing of the data value into the memory array, an ECC decoder to receive a read ECC value and read data value from the memory array and to also receive a read address value; wherein the ECC logic is to detect and correct an error in the read or write address values based on the read ECC value, the read address value, and the read data value; wherein the apparatus is to roll back stored data values of all or a portion of the memory array to an earlier state upon detecting the error in the read or write address values. - View Dependent Claims (16, 17)
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18. One or more non-transitory computer-readable storage mediums having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
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receiving a command to read from a memory array at an address value; reading a data value and an error correction code (ECC) value from the memory array based on the address value, wherein, during a previous write of the data value, the ECC value was generated based on the data value and its write address value; performing a decoding operation using the address value, the data value and the ECC value; and
,identifying one or more errors in the address value or write address value based on the decoding operation; and
,rolling back stored data values of all or a portion of the memory array to an earlier state upon detecting the one or more errors. - View Dependent Claims (19)
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Specification