Chip electronic component

• US 10,319,515 B2
• Filed: 02/18/2016
• Issued: 06/11/2019
• Est. Priority Date: 05/19/2015
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Jung, Jung hyuk, Choi, Woon Chul, Ah, Jun, Park, Myung Jun, Bang, Hye Min
• Primary Examiner(s): Chan, Tszfung J
• Application Number:
  US15/047,214
• Publication Number:
  US 20160343500A1
• Time in Patent Office: 1,209 Days
• Field of Search: 336200, 336232
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 17/04 with magnetic core
• CPC Class Codes: H01F 2017/048 with encapsulating core, e.g. made of resin and magnetic powder
• CPC Class Codes: H01F 27/292 Surface mounted devices
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material

Abstract

A chip electronic component includes a magnetic main body including an insulating substrate and a coil conductor pattern disposed on at least one surface of the insulating substrate, and external electrodes formed on opposite ends of the magnetic main body so as to be connected to an end of the coil conductor pattern. The coil conductor pattern includes a pattern plating layer and a first plating layer disposed on the pattern plating layer, and a thickness of the first plating layer of innermost and outermost coil conductor patterns of the coil conductor pattern is greater than a thickness of the first plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

Claims

1. A chip electronic component comprising:

a magnetic main body including an insulating substrate and a coil conductor pattern disposed on at least one surface of the insulating substrate; and

external electrodes disposed on first and second ends of the magnetic main body so as to be connected to an end of the coil conductor pattern,

wherein the coil conductor pattern includes a pattern plating layer and a first plating layer disposed on the pattern plating layer, and a thickness of the first plating layer of innermost and outermost coil conductor patterns of the coil conductor pattern is greater than a thickness of the first plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns,

the coil conductor pattern further includes a second plating layer disposed on the first plating layer, and

a thickness of the second plating layer of the innermost and outermost coil conductor patterns of the coil conductor pattern is shorter than a thickness of the second plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

2. The chip electronic component of claim 1, wherein thicknesses of the first plating layer of the inner coil conductor patterns are the same.

3. The chip electronic component of claim 1, wherein Wa′

<

Wa, where Wa is a width of a pattern plating layer of innermost and outermost coil conductor patterns of the coil conductor patterns and Wa′

is a width of a pattern plating layer of the inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

4. The chip electronic component of claim 3, wherein widths of the pattern plating layer of the inner coil conductor patterns are the same.

5. The chip electronic component of claim 1, wherein a width of the second plating layer is substantially the same as a width of the first plating layer.

6. The chip electronic component of claim 1, wherein ta′

<

ta, where ta is a thickness of the first plating layer of the innermost and outermost coil conductor patterns of the coil conductor patterns and ta′

is a thickness of the first plating layer of the inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

7. A chip electronic component comprising:

a magnetic main body including an insulating substrate and a coil conductor pattern disposed on at least one surface of the insulating substrate; and

external electrodes formed on first and second ends of the magnetic main body so as to be connected to an end of the coil conductor pattern,

wherein the coil conductor pattern includes a pattern plating layer and a first plating layer disposed on the pattern plating layer, and Wa′

<

Wa, where Wa is a width of a pattern plating layer of innermost and outermost coil conductor patterns of the coil conductor patterns and Wa′

is a width of a pattern plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns,

the coil conductor pattern further includes a second plating layer disposed on the first plating layer, and

a thickness of the second plating layer of the innermost and outermost coil conductor patterns of the coil conductor pattern is shorter than a thickness of the second plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

8. The chip electronic component of claim 7, wherein widths of the pattern plating layer of the inner coil conductor patterns are the same.

9. The chip electronic component of claim 7, wherein a width of the second plating layer is substantially the same as a width of the first plating layer.

10. The chip electronic component of claim 7, wherein ta′

<

ta, where ta is a thickness of the first plating layer of the innermost and outermost coil conductor patterns of the coil conductor patterns and ta′

is a thickness of the first plating layer of the inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

11. A method of manufacturing a chip electronic component, comprising steps of:

forming a coil conductor pattern by forming a pattern plating layer on an insulating substrate and forming a first plating layer on the pattern plating layer, and forming a second plating layer on the first plating layer;

forming a magnetic main body around the coil conductor pattern; and

forming external electrodes on first and second end surfaces of the magnetic main body so as to connect to ends of the coil conductor pattern,

wherein Wa′

<

Wa, where Wa is a width of the pattern plating layer of innermost and outermost coil conductor patterns of the coil conductor patterns and Wa′

is a width of the pattern plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns, and

a thickness of the second plating layer of the innermost and outermost coil conductor patterns of the coil conductor pattern is shorter than a thickness of the second plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

12. The method of manufacturing a chip electronic component of claim 11, wherein a width of the second plating layer is substantially the same as a width of the first plating layer.

13. A method of manufacturing a chip electronic component, comprising steps of:

forming a coil conductor pattern by forming a pattern plating layer on an insulating substrate and forming a first plating layer on the pattern plating layer, and forming a second plating layer on the first plating layer;

forming a magnetic main body around the coil conductor pattern; and

forming external electrodes on first and second end surfaces of the magnetic main body so as to connect to ends of the coil conductor pattern,

wherein ta′

<

ta, where ta is a thickness of a first plating layer of innermost and outermost coil conductor patterns of the coil conductor patterns and ta′

is a thickness of a first plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns,

a thickness of the second plating layer of the innermost and outermost coil conductor patterns of the coil conductor pattern is shorter than a thickness of the second plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.

14. The method of manufacturing a chip electronic component of claim 13, wherein Wa′

<

Wa, where Wa is a width of the pattern plating layer of the innermost and outermost coil conductor patterns of the coil conductor patterns and Wa′

is a width of the pattern plating layer of the inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.