Method for depositing a metal chalcogenide on a substrate by cyclical deposition

• US 10,319,588 B2
• Filed: 10/10/2017
• Issued: 06/11/2019
• Est. Priority Date: 10/10/2017
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Mattinen, Miika, Ritala, Mikko, Leskela, Markku
• Primary Examiner(s): Diallo, Mamadou L
• Application Number:
  US15/729,485
• Publication Number:
  US 20190109002A1
• Time in Patent Office: 609 Days
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/306 AII BVI compounds, where A is Zn, Cd or Hg and B is S, Se or Te
• CPC Class Codes: C23C 16/45553 characterized by the use of precursors specially adapted for ALD
• CPC Class Codes: C23C 16/52 Controlling or regulating the coating process C23C16/45557, C23C16/279 take precedence
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02568 Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/742 the device being a field effect transistor for turn-on or turn-off by field effect H01L29/745, H01L29/749
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for depositing a metal chalcogenide on a substrate by cyclical deposition is disclosed. The method may include, contacting the substrate with at least one metal containing vapor phase reactant and contacting the substrate with at least one chalcogen containing vapor phase reactant. Semiconductor device structures including a metal chalcogenide deposited by the methods of the disclosure are also provided.

Claims

1. A method for depositing a metal chalcogenide on a substrate by cyclical deposition, the method comprising:

contacting the substrate with at least one metal containing vapor phase reactant comprising, a partial chemical structure represented by the formula M-O—

C, wherein a metal (M) atom is bonded to an oxygen (O) atom, and said oxygen (O) atom is bonded to a carbon (C) atom, and wherein M is selected from the group consisting of tin (Sn) and germanium (Ge); and

contacting the substrate with at least one chalcogen containing vapor phase reactant.

2. The method of claim 1, wherein the metal chalcogenide comprises a metal dichalcogenide.

3. The method of claim 1, wherein the at least one chalcogen containing vapor phase reactant comprises S, Se, or Te.

4. The method of claim 1, wherein the metal chalcogenide comprises an oxygen (O) content less than 10 atomic-%.

5. The method of claim 1, wherein the cyclical deposition comprises atomic layer deposition.

6. The method of claim 1, wherein the cyclical deposition comprises cyclical chemical vapor deposition.

7. The method of claim 1, wherein the metal containing vapor phase reactant comprises metal (IV) tert-butoxide (M(O^tBu)₄).

8. The method of claim 1, wherein the tin (Sn) containing vapor phase reactant is represented by the chemical formula Sn(OR)_x, wherein R is a C₁-C₅ alkyl group and x is an integer from 2-6.

9. The method of claim 7, wherein the at least one tin (Sn) containing vapor phase reactant comprises tin (IV) acetate.

10. The method of claim 7, wherein the at least one tin (Sn) containing vapor phase reactant is represented by the partial formula:

11. The method of claim 7, wherein the at least one tin (Sn) containing vapor phase reactant is represented by the partial formula:

12. The method of claim 7, wherein the at least one tin (Sn) containing vapor phase reactant is represented by the partial chemical formula:

L-Sn—

O—

C

wherein a tin (Sn) atom is bonded to an oxygen (O) atom, and said oxygen (O) atom is bonded to a carbon atom (C), and L is a hydrocarbon group.

13. The method of claim 1, wherein the at least one chalcogen containing vapor phase reactant comprises hydrogen sulfide (H₂S), hydrogen selenide (H₂Se), dimethyl sulfide ((CH₃)₂S), or dimethyl telluride (CH₃)₂Te.

14. The method of claim 1, wherein the method comprises at least one deposition cycle in which the substrate is alternately and sequentially contacted with the at least metal containing vapor phase reactant and the at least one chalcogen containing vapor phase reactant.

15. The method of claim 14, wherein the deposition cycle is repeated two or more times.

16. The method of claim 1, further comprising heating the substrate to a temperature of approximately greater than 150°

C.

17. The method of claim 16, further comprising heating the substrate to a temperature of less than approximately 500°

C.

18. The method of claim 1, wherein the metal chalcogenide comprises tin disulfide.

19. The method of claim 1, wherein the metal chalcogenide comprises germanium disulfide.

20. The method of claim 1, further comprising a post-deposition annealing of the metal chalcogenide at a temperature between approximately 150°

C. and approximately 300°

C.

21. The method of claim 20, wherein the post-deposition annealing of the metal chalcogenide is performed in a hydrogen sulfide (H₂S) atmosphere.

22. A semiconductor device structure comprising a metal chalcogenide deposited by the method of claim 1.

23. The semiconductor device structure of claim 22, wherein the metal chalcogenide comprises at least a portion of the channel region in a transistor structure.

24. A reaction system configured to perform the method of claim 1.