Thermal silicon etch

• US 10,319,600 B1
• Filed: 03/12/2018
• Issued: 06/11/2019
• Est. Priority Date: 03/12/2018
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Li, Zihui, Cheng, Rui, Wang, Anchuan, Ingle, Nitin K., Mallick, Abhijit Basu
• Primary Examiner(s): Ahmed, Shamim
• Application Number:
  US15/918,860
• Time in Patent Office: 456 Days
• Field of Search: None
• CPC Class Codes: H01J 37/00 Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof H01J33/00, H01J40/00, H01J41/00, H01J47/00, H01J49/00 take precedence
• CPC Class Codes: H01J 37/32357 Generation remote from the workpiece, e.g. down-stream
• CPC Class Codes: H01J 37/32422 Arrangement for selecting ions or species in the plasma
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01J 37/32724 Temperature
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.

Claims

1. An etching method comprising:

flowing a fluorine-containing precursor into a substrate processing region of a semiconductor processing chamber, wherein a substrate is positioned within the substrate processing region and the substrate comprises silicon and dielectric, wherein the silicon and the dielectric are exposed on sidewalls of a trench formed in stacked alternating layers of the silicon and the dielectric; and

removing silicon from the sidewalls of the trench.

2. The method of claim 1, wherein removing silicon from the sidewalls of the trench comprises laterally etching silicon from the sidewalls of the trench.

3. The method of claim 1, wherein the dielectric is one of silicon oxide or silicon nitride.

4. The method of claim 1, wherein the silicon comprises one of amorphous silicon, single crystal silicon or polysilicon.

5. The method of claim 1, wherein the removal of the silicon removes silicon with a horizontal etch progression.

6. The method of claim 1, wherein the removal of the silicon removes silicon at an etch rate more than twenty times faster than dielectric.

7. The method of claim 1, wherein the removal of the silicon is performed at a substrate temperature of less than 500°

C.

8. The method of claim 1, wherein the removal of the silicon is performed at a partial pressure of fluorine-containing precursor which is more than 1 Torr.

9. The method of claim 1, wherein the stacked alternating layers comprise at least 50 layers of alternating layers of the silicon and the dielectric.

10. The method of claim 1, wherein the trench has an aspect ratio of greater than or about 50:

1.

11. The method of claim 1, wherein a layer of the silicon at an upper region of the trench and a layer of silicon at a lower region of the trench differ in lateral etch amounts by less than about 2 nm.

12. The method of claim 1, wherein the fluorine-containing precursor is one of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, or xenon difluoride.

13. An etching method comprising:

flowing a fluorine-containing precursor into a substrate processing region of a semiconductor processing chamber, wherein a substrate is positioned within the substrate processing region and the substrate comprises polysilicon and dielectric, wherein the polysilicon and the dielectric are exposed on sidewalls of a trench formed in stacked alternating layers of the polysilicon and the dielectric; and

laterally etching the polysilicon from the sidewalls of the trench.

14. The method of claim 13, wherein the lateral removal of polysilicon removes polysilicon with a horizontal etch progression.

15. The method of claim 13, wherein the lateral removal of polysilicon removes polysilicon at an etch rate more than twenty times faster than the dielectric.

16. The method of claim 13, wherein the lateral removal of polysilicon is performed at a temperature of less than 600°

C.

17. The method of claim 13, wherein the lateral removal of polysilicon is performed at a partial pressure of fluorine-containing precursor within the substrate processing region which is more than 1 Torr.

18. The method of claim 13, wherein the trench is characterized by an aspect ratio of greater than or about 50:

1.

19. The method of claim 13, wherein the stacked alternating layers comprise at least 50 layers of alternating layers of the polysilicon and the dielectric.

20. The method of claim 13, wherein a layer of the polysilicon at an upper region of the trench and a layer of silicon at a lower region of the trench differ in lateral etch amounts by less than about 2 nm.