Conditions for burn-in of high power semiconductors

• US 10,319,648 B2
• Filed: 04/17/2018
• Issued: 06/11/2019
• Est. Priority Date: 04/17/2017
• Status: Active Grant

• Current Assignee: Transphorm Technology, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Transphorm, Inc (Kohlberg Kravis Roberts & Company LP)
• Inventors: Smith, Kurt Vernon, Shen, Likun, Rhodes, David Michael, Barr, Ronald Avrom, McKay, James Leroy
• Primary Examiner(s): Booth, Richard A
• Application Number:
  US15/955,515
• Publication Number:
  US 20180301386A1
• Time in Patent Office: 420 Days
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/2642 Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/67271 Sorting devices
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Techniques for improving reliability of III-N devices include holding the III-N devices at a first temperature less than or equal to 30° for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the III-N devices and a first drain-source voltage greater than 0.2 times a break down voltage of the III-N devices; and holding the III-N devices at a second temperature greater than the first temperature for a second period of time while applying a second gate-source voltage lower than a threshold voltage of the III-N devices and a second drain-source voltage greater than 0.2 times a breakdown voltage of the III-N devices. After holding the III-N devices at the first and second temperatures, screening the III-N devices based on electrical performance of one or more parameters of the III-N devices.

Claims

1. A method of testing a plurality of III-N devices each comprising a source, a gate, and a drain, the method comprising:

for each device, holding the device at a first temperature less than or equal to 30°

C. for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the device and a first drain-source voltage greater than 0.2 times a breakdown voltage of the device;

for each device, holding the device at a second temperature greater than the first temperature for a second period of time while applying a second gate-source voltage lower than the threshold voltage of the device and a second drain-source voltage greater than 0.2 times the breakdown voltage of the device;

after holding the devices at the first and second temperatures, testing electrical performance of one or more parameters of each of the devices; and

based on results obtained from the testing, rejecting at least one device of the plurality of devices.

2. The method of claim 1, wherein the first period of time or the second period of time is greater than 24 hours.

3. The method of claim 1, wherein the second temperature is greater than 50°

C.

4. The method of claim 1, wherein each of the devices is rated for operation at a minimum operating temperature, and the first temperature is less than or equal to the minimum operating temperature.

5. The method of claim 1, wherein the second temperature is greater than or equal to a median operating temperature range.

6. The method of claim 1, wherein one of the electrical performance-tested parameters is a dynamic on-resistance;

and

a device is rejected if the dynamic on-resistance is within 10% or greater of a maximum specified dynamic on-resistance.

7. The method of claim 1, wherein one of the electrical performance-tested parameters is an on-resistance;

and

a device is rejected if an increase of the on-resistance is 25% or greater compared to a previous test of the device on-resistance.

8. The method of claim 1, wherein one of the electrical performance-tested parameters is an off-state drain-source leakage;

and

a device is rejected if the off-state drain-source leakage is within 10% or greater of a maximum specified off-state drain-source leakage.

9. The method of claim 1, wherein one of the electrical performance-tested parameters is an off-state drain-source leakage;

and

a device is rejected if the off-state drain-source leakage is greater than 1 μ

A.

10. The method of claim 1, further comprising

holding the device at one or more additional temperatures for corresponding periods of time while the drain-source voltage is greater than 0.2 times the breakdown voltage of the device,

wherein the one or more additional temperatures are different from the first temperature and the second temperature.

11. The method of claim 2, further comprising packaging the plurality III-N devices into an electronic package prior to testing;

wherein

the packaged devices are mounted into a printed circuit board, and the printed circuit board is configured to test the plurality of III-N device simultaneously.

12. The method of claim 11, wherein the first or second drain-source voltage is greater than 400V.

13. A method of assuring quality and reliability of a III-N device, the device including a package, a gate, a source, and a drain, the method comprising:

for a first period of time, applying a first gate-source voltage below a threshold voltage of the device and applying a positive drain-source voltage;

holding the package at a first temperature which is below a median operating temperature range of the device for the first period of time; and

after holding the devices at the first temperature, testing electrical performance of one or more parameters of the device; and

based on results obtained from the testing, rejecting the device if the performance is not within an acceptable range of one or more of the electrical performance-tested parameters.

14. The method of claim 13, further comprising, holding the device at a second temperature which is greater than a median operating temperature range of the device for a second period of time;

and

after holding the device at the second temperature, testing again the electrical performance of one or more parameters of the device; and

based on the results obtained from the testing again, rejecting the device if the performance is not within an acceptable range of one or more of the electrical performance-tested parameters.

15. The method of claim 14, wherein the first period of time is greater than 24 hrs.

16. The method of claim 15, wherein the first period of time is less than 96 hours.

17. The method of claim 14, wherein the positive drain-source voltage is greater than 0.2 times a breakdown voltage of the device.

18. The method of claim 14, wherein one of the electrical performance-tested parameters is an off-state drain-source leakage;

and

a device is rejected if the off-state drain-source leakage is greater than 1 μ

A.

19. The method of claim 14, wherein one of the electrical performance-tested parameters is a dynamic on-resistance;

and

a device is rejected if the dynamic on-resistance is within 10% or greater of a maximum specified dynamic on-resistance.

20. The method of claim 14, wherein the first temperature is below 50°

C.

21. The method of claim 20, wherein the second temperature is greater than 50°

C.

22. A method of testing a wafer including a plurality of III-N electronic devices each comprising a source, a gate, and a drain, the method comprising:

holding the wafer at a first temperature less than or equal to 30°

C. for a first period of time while simultaneously applying to a plurality of the devices a first gate-source voltage lower than a threshold voltage of the device and a first drain-source voltage greater than 0.2 times a breakdown voltage of the device;

holding the wafer at a second temperature greater than the first temperature for a second period of time while simultaneously applying to a plurality of the devices a second gate-source voltage lower than the threshold voltage of the device and a second drain-source voltage greater than 0.2 times the breakdown voltage of the device;

after holding the wafer at the first and second temperatures, testing electrical performance of one or more parameters of each of the devices; and

based on results obtained from the testing, rejecting at least one device on the wafer.

23. The method of claim 22, wherein the first and second periods of time are each greater than 1 hour.

24. The method of claim 23, wherein a testing apparatus has a thermally controlled hot plate, and the wafer is on the hot plate;

wherein

during the first period of time, the hot plate is turned off; and

during the second period of time, the hot plate controls a wafer temperature.

25. The method of claim 24, wherein during the second period of time, the hot plate controls the wafer temperature to greater than 50°

C.

26. The method of claim 22, wherein the rejected devices are inked on the wafer and the non-inked devices are assembled into a discrete electronic package.

27. The method of claim 22, wherein one of the electrical performance-tested parameters is a dynamic on-resistance;

and

a device is rejected if the dynamic on-resistance is within 10% or greater of a maximum specified dynamic on resistance.

28. The method of claim 22, wherein one of the electrical performance-tested parameters is an off-state drain-source leakage:

and

a device is rejected if the off-state drain-source leakage is within 10% or greater of a maximum specified off-state drain-source leakage.

29. The method of claim 22, wherein one of the electrical performance-tested parameters is an on-resistance;

and

a device is rejected if an increase of the on-resistance is 25% or greater compared to a previous test of the device on-resistance.

30. The method of claim 22, wherein one of the electrical performance-tested parameters is an off-state drain-source leakage;

and

a device is rejected if the off-state drain-source leakage is greater than 1 μ

A.

31. A system for testing a plurality of III-N devices, the system comprising:

a testing chamber and a temperature controller;

wherein

the temperature controller is configured to hold the plurality of devices at a first temperature less than or equal to 30°

C. for a first period of time; and

during the first period of time, the testing chamber is configured to apply a first gate-source voltage lower than a threshold voltage of the device and a first drain-source voltage greater than 0.2 times a breakdown voltage of the device; and

the temperature controller is configured to hold the plurality of devices at a second temperature greater than or equal to 30°

C. for a second period of time; and

the during the second period of time, the testing chamber is configured to apply a second gate-source voltage lower than the threshold voltage of the device and a second drain-source voltage greater than 0.2 times the breakdown voltage of the device;

wherein

the first period of time and the second period of time is greater than 1 hour.

32. A method of testing a plurality of III-N devices each comprising a source, a gate, and a drain, the method comprising:

for each device, holding the device at a first temperature for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the device and a first drain-source voltage greater than 0.2 times a breakdown voltage of the device;

for each device, holding the device at a second temperature for a second period of time while applying a second gate-source voltage lower than the threshold voltage of the device and a second drain-source voltage greater than 0.2 times the breakdown voltage of the device, wherein the second temperature is smaller than the first temperature and smaller than 30°

C.;

after holding the devices at the first and second temperatures, testing electrical performance of one or more parameters of each of the devices; and

based on results obtained from the testing, rejecting at least one device of the plurality of devices.

33. The method of claim 32, wherein the first temperature is greater than 50°

C.

34. The method of claim 32, wherein each of the devices is rated for operation at a minimum operating temperature, and the second temperature is smaller than or equal to the minimum operating temperature.

35. The method of claim 32, wherein the first temperature is greater than or equal to a median operating temperature range.