Stacked semiconductor architecture including semiconductor dies and thermal spreaders on a base die

• US 10,319,700 B1
• Filed: 12/30/2017
• Issued: 06/11/2019
• Est. Priority Date: 12/30/2017
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Burton, Edward A.
• Primary Examiner(s): Potter, Roy K
• Application Number:
  US15/859,404
• Publication Number:
  US 20190206836A1
• Time in Patent Office: 528 Days
• Field of Search: 313501
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/171 Disposition
• CPC Class Codes: H01L 2224/17519 including bump connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/433 Auxiliary members in containers characterised by their shape, e.g. pistons
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

Claims

1. A stacked semiconductor architecture for a semiconductor package, comprising:

a base die;

a plurality of stacked semiconductor dies on the base die;

a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies; and

a heat sink disposed on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders, wherein the heat sink is electrically coupled to the base die.

2. The stacked semiconductor architecture of claim 1, further comprising electrical connections between two or more of the base die, the plurality of stacked semiconductor dies, and the plurality of thermal spreaders.

3. The stacked semiconductor architecture of claim 1, further comprising a heat sink disposed on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

4. The stacked semiconductor architecture of claim 3, wherein a thermal interface material (TIM) layer is disposed between:

(i) the heat sink; and

(ii) the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

5. The stacked semiconductor architecture of claim 1, wherein at least one of the thermal spreaders is formed from a metal or a metal alloy.

6. The stacked semiconductor architecture of claim 1, wherein at least one of the thermal spreaders includes a silicon semiconductor die.

7. The stacked semiconductor architecture of claim 1, wherein at least one of the thermal spreaders is formed from a silicon semiconductor die with one or more metal layers formed thereon.

8. A stacked semiconductor architecture for a semiconductor package, comprising:

a base die;

a plurality of stacked semiconductor dies on the base die; and

a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.

9. A method of forming a stacked semiconductor architecture for a semiconductor package, comprising:

disposing a plurality of stacked semiconductor dies on a base die;

disposing a plurality of thermal spreaders on the base die, the plurality of thermal spreaders arranged on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies; and

electrically coupling the base die to the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

10. The method of claim 9, further comprising:

applying a thermal interface material (TIM) layer on the base die in the one or more gaps or in the one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies prior to disposing the plurality of thermal spreaders on the base die.

11. The method of claim 9, further comprising:

applying a thermal interface material (TIM) layer on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

12. The method of claim 11, further comprising:

disposing a heat sink on the exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

13. The method of claim 12, further comprising:

electrically coupling the heat sink to the base die.

14. The method of claim 9, wherein at least one of the thermal spreaders is formed from a metal or a metal alloy.

15. The method of claim 9, wherein at least one of the thermal spreaders includes a silicon semiconductor die.

16. The method of claim 9, wherein at least one of the thermal spreaders is formed from a silicon semiconductor die with one or more metal layers formed thereon.

17. The method of claim 9, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.

18. A semiconductor package, comprising:

a base die;

a plurality of stacked semiconductor dies on the base die;

a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies; and

electrical connections between two or more of the base die, the plurality of stacked semiconductor dies, and the plurality of thermal spreaders.

19. The semiconductor package of claim 18, further comprising a heat sink disposed on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

20. The semiconductor package of claim 19, wherein a thermal interface material (TIM) layer is disposed between:

(i) the heat sink; and

(ii) the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

21. The semiconductor package of claim 19, wherein the heat sink is electrically coupled to the base die.

22. The semiconductor package of claim 18, wherein at least one of the thermal spreaders is formed from a metal or a metal alloy.

23. The semiconductor package of claim 18, wherein at least one of the thermal spreaders includes a silicon semiconductor die.

24. The semiconductor package of claim 18, wherein at least one of the thermal spreaders is formed from a silicon semiconductor die with one or more metal layers formed thereon.

25. The semiconductor package of claim 18, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.