Accommodating imperfectly aligned memory holes
First Claim
1. A method of forming a 3-d flash memory cell, the method comprising:
- placing a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating silicon oxide and silicon nitride slabs and a vertical memory hole having sidewalls lined with a conformal ONO layer, wherein the conformal ONO layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the patterned substrate further comprises a first polysilicon layer formed on the conformal ONO layer, and wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form a ledge;
forming a silicon nitride spacer on the ledge;
removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer;
removing a bottom portion of the conformal ONO layer using a gas-phase etch;
removing the silicon nitride spacer from the ledge using a gas-phase etch; and
forming a second polysilicon layer on the first polysilicon layer.
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Accused Products
Abstract
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.
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Citations
16 Claims
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1. A method of forming a 3-d flash memory cell, the method comprising:
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placing a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating silicon oxide and silicon nitride slabs and a vertical memory hole having sidewalls lined with a conformal ONO layer, wherein the conformal ONO layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the patterned substrate further comprises a first polysilicon layer formed on the conformal ONO layer, and wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form a ledge; forming a silicon nitride spacer on the ledge; removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer; removing a bottom portion of the conformal ONO layer using a gas-phase etch; removing the silicon nitride spacer from the ledge using a gas-phase etch; and forming a second polysilicon layer on the first polysilicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of forming a 3-d flash memory cell, the method comprising:
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placing a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating silicon oxide and silicon nitride slabs and a vertical memory hole having sidewalls lined with a conformal ONO layer, wherein the conformal ONO layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the patterned substrate further comprises a first polysilicon layer formed on the conformal ONO layer;
wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form a ledge;forming sacrificial silicon oxide in the bottom portion of the vertical memory hole; forming conformal silicon nitride on exposed portions of the first polysilicon layer uncovered by the sacrificial silicon oxide; removing the sacrificial silicon oxide; removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer; removing a bottom portion of the conformal ONO layer using a gas-phase etch; removing the conformal silicon nitride; and forming a second polysilicon layer on the first polysilicon layer and making electrical contact between the second polysilicon layer and underlying silicon. - View Dependent Claims (9, 10, 11)
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12. A method of forming a 3-d flash memory cell, the method comprising:
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forming a bottom portion of a compound stack of alternating silicon oxide and silicon nitride slabs; forming a bottom portion of a memory hole through the bottom portion of the compound stack by patterning the bottom portion of the compound stack; filling the bottom portion of the compound stack with doped silicon oxide; forming a top portion of the compound stack of alternating silicon oxide and silicon nitride slabs; forming a top portion of a memory hole through the top portion of the compound stack by patterning the top portion of the compound stack and exposing the doped silicon oxide; and selectively removing the doped silicon oxide with a gas-phase etch which retains material in the alternating silicon oxide and silicon nitride slabs in each of the top portion and the bottom portion, wherein the bottom portion and the top portion of the compound stack are fluidly coupled and the top portion is laterally displaced from the bottom portion. - View Dependent Claims (13, 14, 15, 16)
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Specification