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Accommodating imperfectly aligned memory holes

  • US 10,319,739 B2
  • Filed: 01/29/2018
  • Issued: 06/11/2019
  • Est. Priority Date: 02/08/2017
  • Status: Active Grant
First Claim
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1. A method of forming a 3-d flash memory cell, the method comprising:

  • placing a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating silicon oxide and silicon nitride slabs and a vertical memory hole having sidewalls lined with a conformal ONO layer, wherein the conformal ONO layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the patterned substrate further comprises a first polysilicon layer formed on the conformal ONO layer, and wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form a ledge;

    forming a silicon nitride spacer on the ledge;

    removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer;

    removing a bottom portion of the conformal ONO layer using a gas-phase etch;

    removing the silicon nitride spacer from the ledge using a gas-phase etch; and

    forming a second polysilicon layer on the first polysilicon layer.

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