FinFET device and method of forming same

• US 10,319,832 B2
• Filed: 10/05/2017
• Issued: 06/11/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Li, Chung-Ting, Wu, Bi-Fen, Lu, Jen-Hsiang, Chang, Chih-Hao
• Primary Examiner(s): Malsawma, Lex H
• Application Number:
  US15/726,074
• Publication Number:
  US 20180315831A1
• Time in Patent Office: 614 Days
• Field of Search: None
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Claims

1. A method comprising:

forming a fin extending above an isolation region;

forming a sacrificial gate stack over the fin, the sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall;

forming a first spacer on the first sidewall of the sacrificial gate stack;

forming a second spacer on the second sidewall of the sacrificial gate stack, wherein forming the first spacer and forming the second spacer comprises;

forming a first spacer layer over a top surface and along the first sidewall and the second sidewall of the sacrificial gate stack;

forming a second spacer layer over the first spacer layer; and

removing lateral portions of the second spacer layer, remaining portions of the second spacer layer forming the first spacer and the second spacer;

forming a patterned mask layer having an opening therein over the sacrificial gate stack, the first spacer and the second spacer, the patterned mask layer extending along a top surface and a sidewall of the first spacer, the second spacer being exposed through the opening in the patterned mask layer;

patterning the fin using the patterned mask layer, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin; and

epitaxially growing a source/drain region in the recess.

2. The method of claim 1, wherein the first spacer layer and the second spacer layer comprise different materials.

3. The method of claim 1, further comprising replacing the sacrificial gate stack with a replacement gate stack.

4. The method of claim 3, wherein the replacement gate stack is an active gate stack.

5. The method of claim 3, wherein the replacement gate stack is a dummy gate stack.

6. The method of claim 1, wherein the source/drain region and the fin comprise different semiconductor materials.

7. The method of claim 1, wherein a sidewall of the first spacer and a top surface of the first spacer layer form an angle between about 90 degrees and about 120 degrees.

8. A method comprising:

patterning a substrate to form trenches, the substrate comprising a first semiconductor material;

filling trenches with a dielectric material to form isolation regions;

etching the isolation regions to expose fins;

forming a sacrificial gate stack along sidewalls and over top surfaces of the fins;

depositing a first spacer layer along a sidewall and over a top surface of the sacrificial gate stack and over the top surfaces of the fins;

depositing a second spacer layer over the first spacer layer;

etching the second spacer layer to remove lateral portions of the second spacer layer, remaining portions of the second spacer layer forming gate spacers;

forming a patterned mask over the sacrificial gate stack and the gate spacers, the patterned mask extending over a portion of the first spacer layer disposed over the top surfaces of the fins and not protected by the gate spacers;

etching the first spacer layer and the fins using the patterned mask, the sacrificial gate stack, and the gate spacers as a combined mask to form first recesses in the fins; and

filling the first recesses with a second semiconductor material to form source/drain regions in the first recesses.

9. The method of claim 8, wherein the first spacer layer and the second spacer layer comprise different materials.

10. The method of claim 8, wherein the first semiconductor material is different from the second semiconductor material.

11. The method of claim 8, further comprising:

forming a dielectric layer over the source/drain regions and along the sidewalls of the sacrificial gate stack;

removing the sacrificial gate stack form a second recess in the dielectric layer; and

forming a replacement gate stack in the second recess.

12. The method of claim 11, wherein the replacement gate stack is an active gate stack.

13. The method of claim 11, wherein the replacement gate stack is a dummy gate stack.

14. The method of claim 11, further comprising merging the source/drain regions to form a common source/drain region for the fins.

15. A method comprising:

forming an isolation region over a substrate;

recessing the isolation region to expose a fin;

forming a first sacrificial gate stack over the fin, the first sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall;

forming a second sacrificial gate stack over the fin, the second sacrificial gate stack having a third sidewall and a fourth sidewall opposite the third sidewall;

forming a first spacer on the first sidewall of the first sacrificial gate stack;

forming a second spacer on the second sidewall of the first sacrificial gate stack;

forming a third spacer on the third sidewall of the second sacrificial gate stack;

forming a fourth spacer on the fourth sidewall of the second sacrificial gate stack;

forming a patterned mask layer over the first sacrificial gate stack and the second sacrificial gate stack, the patterned mask layer coving the first spacer, the second spacer and the third spacer, the patterned mask layer exposing the fourth spacer;

patterning the fin using the patterned mask layer, the first sacrificial gate stack, the second sacrificial gate stack, the first spacer, the second spacer, the third spacer and the fourth spacer as a combined mask to form a first recess and a second recess in the fin, the first recess being interposed between the first sacrificial gate stack and the second sacrificial gate stack, the second sacrificial gate stack being interposed between the first recess and the second recess;

epitaxially growing a first source/drain region in the first recess; and

epitaxially growing a second source/drain region in the second recess.

16. The method of claim 15, further comprising replacing the first sacrificial gate stack with a dummy replacement gate stack.

17. The method of claim 15, further comprising replacing the second sacrificial gate stack with an active replacement gate stack.

18. The method of claim 15, wherein a width of the first source/drain region is greater than a width of the second source/drain region.

19. The method of claim 15, wherein the first source/drain region is spaced apart form the second sacrificial gate stack by a first distance, and wherein the second source/drain region is spaced apart form the second sacrificial gate stack by a second distance different from the first distance.

20. The method of claim 19, wherein the first distance is greater than the second distance.