Resistive memory device having a template layer

• US 10,319,907 B1
• Filed: 03/16/2018
• Issued: 06/11/2019
• Est. Priority Date: 03/16/2018
• Status: Active Grant

• Current Assignee: 4D-S, Ltd. (4DS Memory Limited)
• Original Assignee: 4D-S, Ltd. (4DS Memory Limited)
• Inventors: Desu, Seshubabu
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/923,992
• Time in Patent Office: 452 Days
• Field of Search: 365 46, 365 94, 365100, 365129, 365148, 365158, 365163
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/13 Dissociation, i.e. using memory material including molecules which, during a write operation, are dissociated in ions which migrate further in the memory material
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/51 Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/55 Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/021 Formation of switching materials, e.g. deposition of layers
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/828 Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

Claims

1. A memory device, comprising:

a template layer;

a memory layer connected to the template layer, wherein the memory layer has a variable resistance, and wherein the crystalline structure of the memory layer matches the crystalline structure of the template layer; and

a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure.

2. The memory device of claim 1, wherein the conductivity of the template layer is greater than 10×

10⁶ S m<sup>−

1</sup>.

3. The memory device of claim 1, further comprising a retention layer between the memory layer and the top electrode, wherein the retention layer has a variable ionic conductivity, and is configured to selectively resist ionic conduction.

4. The memory device of claim 3, wherein the resistivity of the retention layer is less than 1×

10<sup>−

4</sup> Ohm-m.

5. The memory device of claim 1, wherein a first contact formed at an interface between the template layer and the memory layer is ohmic, and wherein a second contact formed at an interface between the template layer and the top electrode is ohmic.

6. The memory device of claim 1, further comprising:

a first barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the top electrode is between the first barrier layer and the memory layer; and

a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the template layer is between the second barrier layer and the memory layer.

7. The memory device of claim 6, wherein the first and second barrier layers each have a resistivity less than 1E-4 Ohm-m.

8. The memory device of claim 6, further comprising a side barrier layer, wherein the first and second barrier layers and the side barrier layer define an enclosed space, wherein the top electrode and the memory layer are within the space, and wherein ions of the top electrode and the memory layer are confined to the space by the first and second barrier layers and the side barrier layer.

9. A method of manufacturing a memory device, the method comprising:

forming a template layer;

connecting a memory layer to the template layer, wherein the memory layer has a variable resistance, and wherein the crystalline structure of the memory layer matches the crystalline structure of the template layer; and

forming a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure.

10. The method of claim 9, wherein the conductivity of the template layer is greater than 10×

106S m−

1.

11. The method of claim 9, further comprising forming a retention layer between the memory layer and the top electrode, wherein the retention layer has a variable ionic conductivity, and is configured to selectively resist ionic conduction.

12. The method of claim 11, wherein the resistivity of the retention layer is less than 1×

10-4 Ohm-m.

13. The method of claim 9, wherein a first contact formed at an interface between the template and the memory layer is ohmic, and wherein a second contact form at an interface between the template and the top electrode is ohmic.

14. The method of claim 9, further comprising:

forming a first barrier layer, wherein the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough, and wherein the top electrode is between the first barrier layer and the memory layer; and

forming a second barrier layer, wherein the second barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough, and wherein the template layer is between the second barrier layer and the memory layer.

15. The method of claim 14, wherein the first and second barrier layers each have a resistivity less than 1E-4 Ohm-m.

16. The method of claim 14, further comprising forming a side barrier layer, wherein the first and second barrier layers and the side barrier layer define an enclosed space, wherein the top electrode and the memory layer are within the space, and wherein ions of the top electrode and the memory layer are confined to the space by the first and second layers and the side barrier layer.

17. A method of using a memory device, the memory device comprising a template layer, a memory layer connected to the template layer, the memory layer having a variable resistance, wherein the crystalline structure of the memory layer matches the crystalline structure of the template layer, and wherein the memory device further comprises a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, the method comprising:

applying a first voltage difference across the template layer and the top electrode, whereby an electric field is generated in the memory layer, and such that a resistivity state of the memory layer is changed;

applying a second voltage difference across the template layer and the top electrode;

while the second voltage difference is applied, causing a first current to be conducted through the template layer, the memory layer, and the top electrode; and

determining the resistivity state of the memory layer based on the second voltage and the first current.

18. The method of claim 17, wherein the conductivity of the template layer is greater than 10×

106 S m-1.

19. The method of claim 17, wherein the memory device further comprises a retention layer between the memory layer and the top electrode, wherein the retention layer has a variable ionic conductivity, and is configured to selectively resist ionic conduction, and wherein the method further comprises varying the ionic conductivity of the retention layer with the applied first voltage.

20. The method of claim 19, wherein the resistivity of the retention layer is less than 1×

10-4 Ohm-m.

21. The method of claim 17, wherein the memory device further comprises:

a first barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the top electrode is between the first barrier layer and the memory layer; and

a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the template layer is between the second barrier layer and the memory layer, wherein the method further comprises causing the first current to be conducted through the first and second barrier layers.

22. The method of claim 21, wherein the first and second barrier layers each have a resistivity less than 1E-4 Ohm-m.

23. The method of claim 21, wherein the memory device further comprises a side barrier layer, wherein the first and second barrier layers and the side barrier layer define an enclosed space, wherein the top electrode and the memory layer are within the space, and wherein the method further comprises confining ions of the top electrode and the memory layer to the space with the first and second barrier layers and the side barrier layer.