Packet data traffic management apparatus

• US 10,320,713 B2
• Filed: 01/07/2017
• Issued: 06/11/2019
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Innovasic, Inc. (Analog Devices, Inc.)
• Original Assignee: Innovasic, Inc. (Analog Devices, Inc.)
• Inventors: Alsup, Andrew David, Wray, Taylor M, Coonrod, Kurt H
• Primary Examiner(s): Islam, Rownak
• Application Number:
  US15/400,993
• Publication Number:
  US 20170118141A1
• Time in Patent Office: 885 Days
• Field of Search: 370386
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: H04L 47/13 in a LAN segment, e.g. ring or bus
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/251 Cut-through or wormhole routing
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.

Claims

1. A packet data network traffic management device, comprising:

a plurality of ports;

a plurality of micro-controllers, each of said micro-controllers operates to control packet data through a corresponding port of said plurality of ports, each of said micro-controllers is a deterministic micro-controller and comprises a first hardware thread to manage incoming data packets at its said corresponding port and a second hardware thread allocated to managing outgoing data packets at said corresponding port, each of said first and second hardware threads are managed by hardware of the deterministic micro-controller to execute an instruction of the first hardware thread to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread to process an outgoing data packet; and

said plurality of deterministic micro-controllers selectively communicate data packets between said plurality of ports.

2. The packet data network traffic management device of claim 1, comprising:

a single memory configured such that the packet data from each said corresponding port is selectively routed therethrough.

3. The packet data network traffic management device of claim 2, wherein:

each of said first and second hardware threads comprises an independent interface to access said single memory operable such that each of said first and second hardware threads does not interfere with access to said single memory by others of said first and second hardware threads.

4. The packet data network management device of claim 3, comprising:

said single memory provides a first data path to route the packet data from each port of said plurality of ports therethrough; and

a second selectively operable data path disposed between two ports of said plurality of ports.

5. The packet data network management device of claim 3, wherein:

each deterministic micro-controller of said plurality of deterministic micro-controllers comprises a corresponding receive queue and a corresponding transmit queue; and

each said deterministic micro-controller operates to determine that a packet received at its corresponding port is to be transmitted from that port to a port of another deterministic micro-controller of said plurality of deterministic micro-controllers and transfers said packet to said corresponding transmit queue of said another deterministic micro-controller.

6. The packet data network traffic management device of claim 1, comprising:

one port of said plurality of ports is coupleable to a host processor.

7. The packet data network traffic management device of claim 6, wherein:

said packet data network traffic management device supports a plurality of modes of operation on a packet-by-packet basis; and

said mode of operation of said plurality of modes of operation is selected by said host processor.

8. The packet data network traffic management device of claim 7, wherein:

said host processor determines which port or ports of said plurality of ports each data packet originating from said host processor should be transmitted.

9. The packet data network traffic management device of claim 1, comprising:

a plurality of dedicated communication queues organized to provide communication channels between each of said plurality of deterministic micro-controllers; and

said communication channels are utilized to communicate at least one of mode information and traffic control information.

10. The packet data network traffic management device of claim 2, wherein:

said single memory is temporarily utilized at reset of said packet data network traffic management device to receive and temporarily store firmware received via one port of said plurality of ports.

11. The packet data network traffic management device of claim 10, wherein:

said single memory is utilized to provide one or more of maintaining a static forwarding table, maintaining dynamic forwarding table, emulating one or more protocol specific registers, and maintaining lists utilized for program variable maintenance.

12. The packet data network traffic management device of claim 1, comprising:

a first port and a second port of said plurality of ports are each coupleable in an Ethernet network configured as one of a line topology, a ring topology, or a redundant star topology; and

a third port of said plurality of ports is coupleable to a host processor.

13. A method of controlling operation of a packet data network traffic management device, the method comprising:

controlling packet data through multiple ports of the packet data network traffic management device using multiple deterministic microcontrollers, wherein each of the multiple ports associates with a deterministic microcontroller;

managing incoming data packets at a corresponding port of each deterministic microcontroller using a first hardware thread of the deterministic microcontroller;

managing outgoing data packets at the corresponding port of each deterministic microcontroller using a second hardware thread of the deterministic microcontroller;

managing the first hardware thread and the second hardware thread using hardware of the deterministic microcontroller;

executing an instruction of the first hardware thread to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread to process an outgoing data packet; and

selectively communicating data packets between the multiple ports using the multiple deterministic microcontrollers.

14. The method of claim 13, wherein controlling the packet data includes selectively routing the packet data from each port through a single memory.

15. The method of claim 14, wherein managing the incoming data packets and the outgoing data packets includes accessing the single memory using independent memory interfaces for the first hardware thread and the second hardware thread.

16. The method of claim 13, wherein controlling the packet data includes routing the packet data from each port of the multiple ports to a single memory using a first data path of the packet data network traffic management device, and selectively routing the packet data between two Ethernet ports of the multiple ports using a second data path disposed between the two Ethernet ports.

17. The method of claim 13, wherein managing the incoming data packets includes:

determining that a data packet received at the corresponding port of a first deterministic microcontroller is to be transmitted to a corresponding port of a second deterministic microcontroller; and

transferring the data packet to a corresponding transmit queue of the second deterministic microcontroller.

18. A non-transitory computer readable storage medium comprising instructions when executed by a computer processor are configured to cause a packet data network traffic management device to:

cause multiple deterministic microcontrollers to control packet data through multiple ports of the packet data network traffic management device, wherein each of the multiple ports associates with a deterministic microcontroller;

manage, by each deterministic microcontroller of the multiple deterministic microcontrollers, incoming data packets at a corresponding port of the deterministic microcontroller using a first hardware thread of the deterministic microcontroller;

manage, by each deterministic microcontroller of the multiple deterministic microcontrollers, outgoing data packets at the corresponding port of the deterministic microcontroller using a second hardware thread of the deterministic microcontroller;

manage, the first hardware thread and the second hardware thread using hardware of the deterministic microcontroller;

execute an instruction of the first hardware thread of each deterministic microcontroller to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread of each deterministic microcontroller to process an outgoing data packet; and

selectively communicate data packets between the multiple ports using the multiple deterministic microcontrollers.

19. The non-transitory computer readable storage medium of claim 18, including instructions configured to cause the first hardware thread of the deterministic microcontroller of the multiple deterministic microcontrollers to selectively begin routing of the incoming data packet on a first or a second data path before receiving of the incoming data packet at a first port is completed.

20. The non-transitory computer readable storage medium of claim 18, including instructions configured to cause the first hardware thread of the deterministic microcontroller of the multiple deterministic microcontrollers to selectively begin routing of the incoming data packet to a second port of the multiple ports for transmitting prior to a header of the incoming data packet being written to packet memory.