Packet data traffic management apparatus
First Claim
Patent Images
1. A packet data network traffic management device, comprising:
- a plurality of ports;
a plurality of micro-controllers, each of said micro-controllers operates to control packet data through a corresponding port of said plurality of ports, each of said micro-controllers is a deterministic micro-controller and comprises a first hardware thread to manage incoming data packets at its said corresponding port and a second hardware thread allocated to managing outgoing data packets at said corresponding port, each of said first and second hardware threads are managed by hardware of the deterministic micro-controller to execute an instruction of the first hardware thread to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread to process an outgoing data packet; and
said plurality of deterministic micro-controllers selectively communicate data packets between said plurality of ports.
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Abstract
A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.
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Citations
20 Claims
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1. A packet data network traffic management device, comprising:
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a plurality of ports; a plurality of micro-controllers, each of said micro-controllers operates to control packet data through a corresponding port of said plurality of ports, each of said micro-controllers is a deterministic micro-controller and comprises a first hardware thread to manage incoming data packets at its said corresponding port and a second hardware thread allocated to managing outgoing data packets at said corresponding port, each of said first and second hardware threads are managed by hardware of the deterministic micro-controller to execute an instruction of the first hardware thread to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread to process an outgoing data packet; and said plurality of deterministic micro-controllers selectively communicate data packets between said plurality of ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of controlling operation of a packet data network traffic management device, the method comprising:
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controlling packet data through multiple ports of the packet data network traffic management device using multiple deterministic microcontrollers, wherein each of the multiple ports associates with a deterministic microcontroller; managing incoming data packets at a corresponding port of each deterministic microcontroller using a first hardware thread of the deterministic microcontroller; managing outgoing data packets at the corresponding port of each deterministic microcontroller using a second hardware thread of the deterministic microcontroller; managing the first hardware thread and the second hardware thread using hardware of the deterministic microcontroller; executing an instruction of the first hardware thread to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread to process an outgoing data packet; and selectively communicating data packets between the multiple ports using the multiple deterministic microcontrollers. - View Dependent Claims (14, 15, 16, 17)
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18. A non-transitory computer readable storage medium comprising instructions when executed by a computer processor are configured to cause a packet data network traffic management device to:
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cause multiple deterministic microcontrollers to control packet data through multiple ports of the packet data network traffic management device, wherein each of the multiple ports associates with a deterministic microcontroller; manage, by each deterministic microcontroller of the multiple deterministic microcontrollers, incoming data packets at a corresponding port of the deterministic microcontroller using a first hardware thread of the deterministic microcontroller; manage, by each deterministic microcontroller of the multiple deterministic microcontrollers, outgoing data packets at the corresponding port of the deterministic microcontroller using a second hardware thread of the deterministic microcontroller; manage, the first hardware thread and the second hardware thread using hardware of the deterministic microcontroller; execute an instruction of the first hardware thread of each deterministic microcontroller to process an incoming data packet on alternating clock cycles with an instruction of the second hardware thread of each deterministic microcontroller to process an outgoing data packet; and selectively communicate data packets between the multiple ports using the multiple deterministic microcontrollers. - View Dependent Claims (19, 20)
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Specification