Microcontroller and method for manufacturing the same

• US 10,324,521 B2
• Filed: 10/21/2016
• Issued: 06/18/2019
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nishijima, Tatsuji, Kobayashi, Hidetomo, Atsumi, Tomoaki, Kato, Kiyoshi, Yamazaki, Shunpei
• Primary Examiner(s): Brown, Michael J
• Application Number:
  US15/299,579
• Publication Number:
  US 20170038826A1
• Time in Patent Office: 970 Days
• Field of Search: 713300, 713320
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Claims

1. A semiconductor device comprising:

a CPU;

a controller;

a first circuit;

a second circuit in the CPU, the second circuit including a first nonvolatile memory;

a third circuit electrically connected to the first circuit, the third circuit including a second nonvolatile memory; and

a power gate configured to supply power to the CPU, the first circuit, the second circuit and the third circuit,

wherein the semiconductor device is configured to be in an operation mode,

wherein the operation mode includes at least;

a first mode, the first mode being a mode where the CPU, the first circuit, the second circuit, the third circuit and the controller operate;

a second mode, the second mode being a mode where the first circuit, the third circuit and the controller operate; and

a third mode, the third mode being a mode where the controller operates,

wherein the semiconductor device is configured to shift from the first mode to one of the second mode and the third mode by an instruction of the CPU,

wherein the semiconductor device is configured to shift from the second mode to the first mode by the controller in accordance with a first signal supplied from the first circuit,

wherein the semiconductor device is configured to shift from the third mode to the first mode by the controller in accordance with a second signal supplied to the controller, and

wherein each of the first nonvolatile memory and the second nonvolatile memory includes a first transistor having a channel formation region comprising a first multilayer film.

2. The semiconductor device according to claim 1,

wherein the second circuit and the third circuit each further comprises

a first volatile memory.

3. The semiconductor device according to claim 2,

wherein the first multilayer film has a structure in which a first oxide layer, an oxide semiconductor layer, and a second oxide layer are stacked in number order, and

wherein the first oxide layer has a larger energy gap than the oxide semiconductor layer.

4. The semiconductor device according to claim 3, wherein the first multilayer film comprises indium, gallium, and zinc.

5. The semiconductor device according to claim 3,

wherein the first oxide layer or the second oxide layer comprises indium more than or equal to 1.5 times of the amount of the oxide semiconductor layer interposed between the first oxide layer and the second oxide layer.

6. The semiconductor device according to claim 2,

wherein each of the first nonvolatile memory and the second nonvolatile memory is configured to back up a data stored in the first volatile memory before power supply is stopped by the power gate, and

wherein the data backed up in each of the first nonvolatile memory and the second nonvolatile memory is written into the first volatile memory in a case where power supply is started again by the power gate.

7. The semiconductor device according to claim 1,

wherein the CPU and the second circuit do not operate in the second mode, and

wherein the CPU, the second circuit, the first circuit, and the third circuit do not operate in the third mode.

8. The semiconductor device according to claim 1, further comprising:

an I/O port;

a fourth circuit electrically connected to the I/O port;

a comparator; and

a fifth circuit electrically connected to the comparator,

wherein the I/O port, the fourth circuit, the comparator, and the fifth circuit operate in the first mode, and do not operate in the second and third modes.

9. The semiconductor device according to claim 1, further comprising:

an interrupt controller; and

a sixth circuit electrically connected to the interrupt controller,

wherein the interrupt controller and the sixth circuit operate in the first mode, and do not operate in the second and third modes.

10. The semiconductor device according to claim 1, further comprising:

an interrupt controller; and

a sixth circuit electrically connected to the interrupt controller,

wherein the interrupt controller and the sixth circuit operate in the first mode, and do not operate in the second and third modes, and

wherein the sixth circuit comprises;

a second volatile memory; and

a third nonvolatile memory comprising a second transistor,

wherein a channel formation region of the second transistor comprises a second multilayer film.

11. The semiconductor device according to claim 1, further comprising:

a RAM electrically connected to the CPU,

wherein the RAM comprising a third transistor, and

wherein a channel formation region of the third transistor comprises a third multilayer film.

12. The semiconductor device according to claim 1, wherein the first circuit is configured to output the first signal at regular intervals.

13. A semiconductor device comprising:

a CPU;

a controller;

a first circuit;

a second circuit in the CPU, the second circuit including a first nonvolatile memory;

a third circuit electrically connected to the first circuit, the third circuit including a second nonvolatile memory; and

a power gate configured to supply power to the CPU, the first circuit, the second circuit and the third circuit,

wherein the semiconductor device is configured to be in an operation mode,

wherein the operation mode includes at least;

a first mode, the first mode being a mode where the CPU, the first circuit, the second circuit, the third circuit and the controller operate;

a second mode, the second mode being a mode where the first circuit, the third circuit and the controller operate and the CPU and the second circuit do not operate; and

a third mode, the third mode being a mode where the controller operates and the CPU, the second circuit, the first circuit, and the third circuit do not operate,

wherein each of the first nonvolatile memory and the second nonvolatile memory includes a first transistor having a channel formation region comprising a first multilayer film.

14. The semiconductor device according to claim 13,

wherein the second circuit and the third circuit each further comprises a first volatile memory.

15. The semiconductor device according to claim 14,

wherein the first multilayer film has a structure in which a first oxide layer, an oxide semiconductor layer, and a second oxide layer are stacked in number order, and

wherein the first oxide layer has a larger energy gap than the oxide semiconductor layer.

16. The semiconductor device according to claim 15, wherein the first multilayer film comprises indium, gallium, and zinc.

17. The semiconductor device according to claim 15,

wherein the first oxide layer or the second oxide layer comprises indium more than or equal to 1.5 times of the amount of the oxide semiconductor layer interposed between the first oxide layer and the second oxide layer.

18. The semiconductor device according to claim 14,

wherein each of the first nonvolatile memory and the second nonvolatile memory is configured to back up a data stored in the first volatile memory before power supply is stopped by the power gate, and

wherein the data backed up in each of the first nonvolatile memory and the second nonvolatile memory is written into the first volatile memory in a case where power supply is started again by the power gate.

19. The semiconductor device according to claim 13, further comprising:

an I/O port;

a fourth circuit electrically connected to the I/O port;

a comparator; and

a fifth circuit electrically connected to the comparator,

wherein the I/O port, the fourth circuit, the comparator, and the fifth circuit operate in the first mode, and do not operate in the second and third modes.

20. The semiconductor device according to claim 13, further comprising:

an interrupt controller; and

a sixth circuit electrically connected to the interrupt controller,

wherein the interrupt controller and the sixth circuit operate in the first mode, and do not operate in the second and third modes.

21. The semiconductor device according to claim 13, further comprising:

an interrupt controller; and

a sixth circuit electrically connected to the interrupt controller,

wherein the interrupt controller and the sixth circuit operate in the first mode, and do not operate in the second and third modes, and

wherein the sixth circuit comprises;

a second volatile memory; and

a third nonvolatile memory comprising a second transistor,

wherein a channel formation region of the second transistor comprises a second multilayer film.

22. The semiconductor device according to claim 13, further comprising:

a RAM electrically connected to the CPU,

wherein the RAM comprising a third transistor, and

wherein a channel formation region of the third transistor comprises a third multilayer film.