Flash memory controller and memory device for accessing flash memory module, and associated method

• US 10,324,789 B2
• Filed: 08/29/2018
• Issued: 06/18/2019
• Est. Priority Date: 08/10/2015
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Yang, Tsung-Chieh
• Primary Examiner(s): Vallecillo, Kyle
• Application Number:
  US16/115,570
• Publication Number:
  US 20180373593A1
• Time in Patent Office: 293 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method for accessing a flash memory module includes: sequentially writing Nth−(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth−(N+K)th data to generate Nth−(N+K)th ECCs, respectively, where the Nth−(N+K)th ECCs are used to correct errors of the Nth−(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth−(N+K)th ECCs to generate the (N+K+1)th ECC.

Claims

1. A method for accessing a flash memory module, comprising:

encoding Nth data to generate an Nth error correction code (ECC), wherein the Nth ECC is used to correct errors of the Nth data, and N is a positive integer;

writing the Nth data into the flash memory module;

writing the Nth ECC into the flash memory module;

when the Nth data is successfully written into the flash memory module, deleting at least a portion of the Nth ECC, but the Nth data is still valid in the flash memory module;

encoding (N+1)th−

(N+M)th data to generate (N+1)th−

(N+M)th ECCs, respectively, wherein the (N+1)th−

(N+M)th ECCs are used to correct errors of the (N+1)th−

(N+M)th data, respectively, and M is a positive integer;

writing the (N+1)th−

(N+M)th data into the flash memory module;

writing the (N+1)th−

(N+M)th ECCs into the flash memory module; and

when the (N+M)th data is successfully written into the flash memory module, deleting the Nth−

(N+M)th ECCs, but the Nth−

(N+M)th data are still valid in the flash memory module.

2. The method of claim 1, wherein the Nth−

(N+M)th data are written into different word lines of the flash memory module.

3. The method of claim 1, wherein the flash memory module comprises a plurality of chips, and a super block is configured to include one block within each chip, the Nth data is written into a first page of the super block of the flash memory module, and the (N+M)th data is written into a last page of the super block of the flash memory module.

4. The method of claim 1, wherein the steps of writing the Nth ECC and writing the (N+1)th−

(N+M)th ECCs into the flash memory module comprises;

writing the Nth−

(N+M)th ECCs into a specific block of the flash memory module.

5. The method of claim 4, wherein the step of deleting the Nth−

(N+M)th ECCs comprises;

when it is determined that the (N+M)th data is successfully written into the flash memory module, erasing the specific block to delete the Nth−

(N+M)th ECCs.

6. The method of claim 1, when the (N+M)th data is successfully written into the flash memory module, before the Nth−

(N+M)th ECCs are deleted, reading (N+M−

P)th−

(N+M)th ECCs from a block and writing the (N+M−

P)th−

(N+M)th ECCs into another block, wherein P is a positive integer less than M.

7. The method of claim 6, wherein P is equal to a quantity of word lines within a word line group.

8. A flash memory controller, arranged to access a flash memory module, and comprising:

a memory, arranged to store a program code;

a microprocessor, arranged to execute the program code, to control access of the flash memory module; and

an encoder;

wherein the encoder encodes Nth data to generate an Nth error correction code (ECC), wherein the Nth ECC is used to correct errors of the Nth data, and N is a positive integer; and

the microprocessor writes the Nth data and the Nth ECC into the flash memory module; and

when the Nth data is successfully written into the flash memory module, the microprocessor deletes at least a portion of the Nth ECC, but the Nth data is still valid in the flash memory module;

wherein the encoder encodes (N+1)th−

(N+M)th data to generate (N+1)th−

(N+M)th ECCs, respectively, wherein the (N+1)th−

(N+M)th ECCs are used to correct errors of the (N+1)th−

(N+M)th data, respectively, and M is a positive integer; and

the microprocessor writes the (N+1)th−

(N+M)th data and the (N+1)th−

(N+M)th ECCs into the flash memory module; and

when the (N+M)th data is successfully written into the flash memory module, the microprocessor deletes the Nth−

(N+M)th ECCs, but the Nth−

(N+M)th data are still valid in the flash memory module.

9. The flash memory controller of claim 8, wherein the Nth−

(N+M)th data are written into different word lines of the flash memory module.

10. The flash memory controller of claim 8, wherein the flash memory module comprises a plurality of chips, and a super block is configured to include one block within each chip, the Nth data is written into a first page of the super block of the flash memory module, and the (N+M)th data is written into a last page of the super block of the flash memory module.

11. The flash memory controller of claim 8, wherein the microprocessor writes the Nth−

(N+M)th ECCs into a specific block of the flash memory module.

12. The flash memory controller of claim 11, wherein when it is determined that the (N+M)th data is successfully written into the flash memory module, the microprocessor erases the specific block to delete the Nth−

(N+M)th ECCs.

13. The flash memory controller of claim 8, when the (N+M)th data is successfully written into the flash memory module, before the Nth−

(N+M)th ECCs are deleted, the microprocessor reads (N+M−

P)th−

(N+M)th ECCs from a block and writes the (N+M−

P)th−

(N+M)th ECCs into another block, wherein P is a positive integer less than M.

14. The flash memory controller of claim 13, wherein P is equal to a quantity of word lines within a word line group.

15. A memory apparatus, comprising:

a flash memory module; and

a flash memory controller, arranged to access the flash memory module;

wherein the flash memory controller encodes Nth data to generate an Nth error correction code (ECC), wherein the Nth ECC is used to correct errors of the Nth data, and N is a positive integer; and

the flash memory controller writes the Nth data and the Nth ECC into the flash memory module; and

when the Nth data is successfully written into the flash memory module, the flash memory controller deletes at least a portion of the Nth ECC, but the Nth data is still valid in the flash memory module;

wherein the flash memory controller encodes (N+1)th−

(N+M)th data to generate (N+1)th−

(N+M)th ECCs, respectively, wherein the (N+1)th−

(N+M)th ECCs are used to correct errors of the (N+1)th−

(N+M)th data, respectively, and M is a positive integer; and

the flash memory controller writes the (N+1)th−

(N+M)th data and the (N+1)th−

(N+M)th ECCs into the flash memory module; and

when the (N+M)th data is successfully written into the flash memory module, the flash memory controller deletes the Nth−

(N+M)th ECCs, but the Nth−

(N+M)th data are still valid in the flash memory module.