Associating a processing thread and memory section to a memory device
First Claim
1. A storage unit of a dispersed storage network (DSN), the storage unit comprises:
- a network interface;
a plurality of main memories; and
a plurality of processing modules, wherein the plurality of processing modules are operably coupled to the network interface and the plurality of main memories, wherein a first processing module of the plurality of processing modules is operable to;
receive access requests, wherein an access request of the access requests includes a logical DSN address and a storage function;
perform logical to physical address conversions of logical DSN addresses of the access requests to produce physical addresses of a plurality of main memories of the storage unit;
for a first access request of the access requests;
identify a first main memory from the plurality of main memories based on the logical to physical address resulting from the physical address conversion of a first logical DSN address of the first access request;
identify a first processing thread of a plurality of processing threads based on an allocation of the plurality of processing threads to the plurality of main memories, wherein the allocation of the plurality of processing threads to the plurality of main memories includes;
allocating the first processing thread to a first main memory of the plurality of main memories, wherein the first main memory is paired with a first subset of memory devices of a plurality of memory devices;
allocating a second processing thread to the first main memory of the plurality of main memories wherein the first main memory is paired with a second subset of memory devices of the plurality of memory devices; and
allocating a third processing thread to a second main memory of the plurality of main memories wherein the second main memory is paired with a third subset of memory devices of the plurality of memory devices; and
instruct the first processing thread to execute a plurality of tasks of the first access request to fulfill the first access request.
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Accused Products
Abstract
A method begins by a storage unit of a dispersed storage network (DSN) receiving access requests which include a logical DSN address and a storage function. The method continues with a first processing module of the storage unit performing logical to physical address conversions of logical DSN addresses of the access requests to physical addresses of a plurality of main memories. For a first access request of the access requests, the method continues with the first processing module identifying a first main memory based on the physical address resulting from the physical address conversion. The method continues with the first processing module identifying a first processing thread of a plurality of processing threads based on allocation of the plurality of processing threads to the plurality of main memories. The method continues with the first processing thread executing tasks of the first access request to fulfill the first access request.
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Citations
14 Claims
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1. A storage unit of a dispersed storage network (DSN), the storage unit comprises:
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a network interface; a plurality of main memories; and a plurality of processing modules, wherein the plurality of processing modules are operably coupled to the network interface and the plurality of main memories, wherein a first processing module of the plurality of processing modules is operable to; receive access requests, wherein an access request of the access requests includes a logical DSN address and a storage function; perform logical to physical address conversions of logical DSN addresses of the access requests to produce physical addresses of a plurality of main memories of the storage unit; for a first access request of the access requests; identify a first main memory from the plurality of main memories based on the logical to physical address resulting from the physical address conversion of a first logical DSN address of the first access request; identify a first processing thread of a plurality of processing threads based on an allocation of the plurality of processing threads to the plurality of main memories, wherein the allocation of the plurality of processing threads to the plurality of main memories includes; allocating the first processing thread to a first main memory of the plurality of main memories, wherein the first main memory is paired with a first subset of memory devices of a plurality of memory devices; allocating a second processing thread to the first main memory of the plurality of main memories wherein the first main memory is paired with a second subset of memory devices of the plurality of memory devices; and allocating a third processing thread to a second main memory of the plurality of main memories wherein the second main memory is paired with a third subset of memory devices of the plurality of memory devices; and instruct the first processing thread to execute a plurality of tasks of the first access request to fulfill the first access request. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprises:
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receiving, by a storage unit of a dispersed storage network (DSN), access requests, wherein an access request of the access requests includes a logical DSN address and a storage function; performing, by a first processing module of a plurality of processing modules of the storage unit, logical to physical address conversions of logical DSN addresses of the access requests to produce physical addresses of a plurality of main memories of the storage unit; for a first access request of the access requests; identifying, by the first processing module, a first main memory from the plurality of main memories based on the physical address resulting from the logical to physical address conversion of a first logical DSN address of the first access request; identifying, by the first processing module, a first processing thread of a plurality of processing threads based on an allocation of the plurality of processing threads to the plurality of main memories, wherein the allocation of the plurality of processing threads to the plurality of main memories includes; allocating the first processing thread to a first main memory of the plurality of main memories, wherein the first main memory is paired with a first subset of memory devices of a plurality of memory devices; allocating a second processing thread to the first main memory of the plurality of main memories wherein the first main memory is paired with a second subset of memory devices of the plurality of memory devices; and allocating a third processing thread to a second main memory of the plurality of main memories wherein the second main memory is paired with a third subset of memory devices of the plurality of memory devices; and executing, by the first processing thread, a plurality of tasks of the first access request to fulfill the first access request. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification