Memory circuit with integrated processor
First Claim
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1. A memory circuit comprising:
- a memory array comprising one or more memory banks;
a first processor; and
a processor control interface for receiving data processingcommands directed to the first processor from a central processor, wherein the processor control interface includes a set of control registers accessible within an address space of the memory circuit and wherein the processor control interface is configured to indicate through the control registers to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor, and wherein the processor control interface does not comprise any dedicated control line for collision arbitration between the first processor and the central processor;
wherein the memory circuit is a dynamic random access memory circuit further comprising a refresh control circuit configured;
to receive, from the central processor, refresh transactions for performing data refresh operations in at least one memory bank of the memory array;
to determine whether the at least one memory bank is being accessed by the first processor, and if so, to delay a start time of the data refresh operation.
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Abstract
A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
13 Citations
12 Claims
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1. A memory circuit comprising:
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a memory array comprising one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, wherein the processor control interface includes a set of control registers accessible within an address space of the memory circuit and wherein the processor control interface is configured to indicate through the control registers to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor, and wherein the processor control interface does not comprise any dedicated control line for collision arbitration between the first processor and the central processor; wherein the memory circuit is a dynamic random access memory circuit further comprising a refresh control circuit configured; to receive, from the central processor, refresh transactions for performing data refresh operations in at least one memory bank of the memory array; to determine whether the at least one memory bank is being accessed by the first processor, and if so, to delay a start time of the data refresh operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of accessing a memory circuit comprising
a memory array having one or more memory banks; -
a first processor; and a processor control interface comprising a set of control registers accessible within an address space of the memory circuit, the method comprising; receiving, by the processor control interface, data processing commands directed to the first processor from a central processor; indicating, by one of the control registers of the processor control interface (904) to the central processor, and without using any dedicated control line for collision arbitration between the first processor and the central processor, when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor; wherein the memory circuit is a dynamic random access memory circuit, the method further comprising; receiving, by a refresh control circuit, a refresh transaction for performing a data refresh operation in a memory bank of the memory array; determining, by the refresh control circuit, whether the memory bank is being accessed by the first processor, and if so, delaying a start time of the data refresh operation. - View Dependent Claims (12)
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Specification