Orthogonal differential vector signaling codes with embedded clock

• US 10,324,876 B2
• Filed: 08/21/2018
• Issued: 06/18/2019
• Est. Priority Date: 11/25/2015
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): Misiura, Brian T
• Application Number:
  US16/107,839
• Publication Number:
  US 20180357191A1
• Time in Patent Office: 301 Days
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Claims

1. A method comprising:

generating, using a plurality of sets of output driver slices, a plurality of analog output signals corresponding to symbols of a data-modulated codeword of a vector signaling code, each analog output signal generated by a respective set of output driver slices receiving a respective data-modulated codeword encoded input;

generating, using a plurality of sets of clock-modulated driver slices, a plurality of signals of a clock-modulated subchannel onto the wires of the multi-wire bus, each signal of the plurality of signals of the clock-modulated subchannel driven by a respective set of clock-modulated driver slices receiving a respective clock-modulated subchannel input;

forming signals of an asynchronous-transmit codeword on each wire of the multi-wire bus, each signal of the asynchronous-transmit codeword formed as an analog summation of (i) an analog output signal of the plurality of analog output signals and (ii) a corresponding signal of the plurality of signals of clock-modulated subchannel; and

transmitting the signals of the asynchronous-transmit codeword over the multi-wire bus.

2. The method of claim 1, wherein the respective clock-modulated subchannel input is derived from a clock signal and wherein the respective data-modulated codeword encoded input is derived from one or more data signals.

3. The method of claim 2, wherein the clock signal has a phase offset with respect to a phase of the one or more data signals.

4. The method of claim 3, wherein the phase offset is a half-unit interval delay with respect to the phase one or more data signals.

5. The method of claim 2, wherein the one or more data signals are synchronous.

6. The method of claim 2, wherein the one or more data signals correspond to a single data phase of a plurality of data phases.

7. The method of claim 1, wherein each set of output driver slices of the plurality of output driver slices further comprises one or more output driver slices for receiving a data-modulated codeword encoded input derived from symbols transmitted in a previous unit interval.

8. The method of claim 1, wherein each set of output driver slices of the plurality of output driver slices comprises one or more output driver slices for receiving a data-modulated codeword encoded input derived from symbols to be transmitted in a subsequent unit interval.

9. The method of claim 1, wherein the asynchronous-transmit codeword is a permutation of {+1, −

⅓

, −

⅓

, −

⅓

} or {−

1, ⅓

, ⅓

, ⅓

}.

10. The method of claim 1, wherein the respective data-modulated codeword encoded input is a multi-bit input indicative of a symbol value of at least a quaternary alphabet.

11. An apparatus comprising:

a plurality of sets of output driver slices, each set of output driver slices of the plurality of output driver slices configured to receive a respective data-modulated codeword encoded input and to responsively generate an analog output signal of a plurality of analog output signals on respective wires a multi-wire bus, the analog output signals corresponding to respective symbols of a data-modulated codeword of a vector signaling code; and

a plurality of sets of clock-modulated driver slices, each set of clock-modulated driver slices configured to receive a respective clock-modulated subchannel input and to responsively generate a plurality of signals of a clock-modulated subchannel on respective wires of the multi-wire bus;

the multi-wire bus configured to form signals of an asynchronous-transmit codeword, each signal of the asynchronous codeword formed as an analog summation of (i) an analog output signal of the plurality of analog output signals and (ii) a corresponding signal of the plurality of signals of the clock-modulated subchannel, the signals of the asynchronous-transmit codeword transmitted over respective wires of the multi-wire bus.

12. The apparatus of claim 11, wherein the respective clock-modulated subchannel input is derived from a clock signal and wherein the respective data-modulated codeword encoded input is derived from one or more data signals.

13. The apparatus of claim 12, wherein the clock signal has a phase offset with respect to a phase of the one or more data signals.

14. The apparatus of claim 13, wherein the phase offset is a half-unit interval delay with respect to the phase of the one or more data signals.

15. The apparatus of claim 12, wherein the one or more data signals are synchronous.

16. The apparatus of claim 12, wherein the one or more data signals correspond to a single data phase of a plurality of data phases.

17. The apparatus of claim 11, wherein each set of output driver slices of the plurality of output driver slices further comprises one or more output driver slices configured to receive a data-modulated codeword encoded input derived from symbols transmitted in a previous unit interval.

18. The apparatus of claim 11, wherein each set of output driver slices of the plurality of output driver slices further comprises one or more output driver slices configured to receive a data-modulated codeword encoded input derived from symbols to be transmitted in a subsequent unit interval.

19. The apparatus of claim 11, wherein the asynchronous-transmit codeword is a permutation of {1, −

⅓

, −

⅓

, −

⅓

} or {−

1, ⅓

, ⅓

, ⅓

}.

20. The apparatus of claim 11, wherein the respective data-modulated codeword encoded input is a multi-bit input indicative of a symbol value of at least a quaternary alphabet.