Erase page check

• US 10,325,670 B2
• Filed: 09/12/2018
• Issued: 06/18/2019
• Est. Priority Date: 08/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Luo, Ting, Stoller, Scott Anthony, Thomson, Preston, Batutis, Devin, Singidi, Harish Reddy, Tanpairoj, Kulachet
• Primary Examiner(s): Tran, Uyen B
• Application Number:
  US16/129,422
• Publication Number:
  US 20190066817A1
• Time in Patent Office: 279 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention

Abstract

Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

Claims

1. A method performed by a NAND memory device, the method comprising:

identifying a NAND memory cell of the memory device to test for an incomplete programming, the memory cell configured as a multi-level cell;

shifting a read voltage used to read a first portion of the memory cell a predetermined magnitude toward zero, the read voltage for the first portion having a lowest read voltage of a plurality of read voltages used to read other portions of the memory cell;

reading a value in the first portion of the memory cell using the shifted read voltage;

determining that the memory cell was incompletely programmed based upon the value;

in response to determining that the memory cell was incompletely programmed, mark the memory cell as incompletely programmed; and

wherein shifting the read voltage and reading the value is a user-mode read operation.

2. The method of claim 1, wherein the first portion is one of:

a least significant bit or a most significant bit of the value.

3. The method of claim 1, further comprising:

detecting an asynchronous power loss based upon determining that a shut-down indicator is not present and identifying the memory cell responsive to detecting the asynchronous power loss.

4. The method of claim 3, further comprising:

receiving an indication that a synchronous shut down is in process;

responsive to the indication that the synchronous shut down is in process, setting a shut-down indicator flag;

upon a subsequent power up, detecting that the shut down indicator flag is set; and

responsive to detecting that the shut down indicator flag is set, refraining from testing memory cells for incomplete programming.

5. The method of claim 1, wherein identifying the memory cell of the memory device comprises finding a last fully written memory cell.

6. The method of claim 1, wherein the memory cell is capable of storing one of:

2 bits, 3 bits or 4 bits of data.

7. A memory device comprising:

a plurality of NAND memory cells; and

a controller, the controller configured to perform operations comprising;

identifying a first NAND memory cell of the plurality of NAND memory cells to test for an incomplete programming, the first memory cell configured as a multi-level cell;

shifting a read voltage used to read a first portion of the first memory cell a predetermined magnitude toward zero, the read voltage for the first portion having a lowest read voltage of a plurality of read voltages used to read other portions of the first memory cell;

reading a value in the first portion of the first memory cell using the shifted read voltage;

determining that the memory cell was incompletely programmed based upon the value;

in response to determining that the memory cell was incompletely programmed, mark the memory cell as incompletely programmed; and

wherein shifting the read voltage and reading the value is a user-mode read operation.

8. The memory device of claim 7, wherein the first portion is one of:

a least significant bit or a most significant bit of the value.

9. The memory device of claim 7, wherein the operations further comprise:

detecting an asynchronous power loss based upon determining that a shut-down indicator is not present and identifying the first memory cell responsive to detecting the asynchronous power loss.

10. The memory device of claim 9, wherein the operations further comprise:

receiving an indication that a synchronous shut down is in process;

responsive to the indication that the synchronous shut down is in process, setting a shut-down indicator flag;

upon a subsequent power up, detecting that the shut down indicator flag is set; and

responsive to detecting that the shut down indicator flag is set, refraining from testing memory cells for incomplete programming.

11. The memory device of claim 7, wherein the operations of identifying the memory cell of the memory device comprises finding a last fully written memory cell.

12. The memory device of claim 7, wherein the first memory cell is capable of storing one of:

2 bits, 3 bits or 4 bits of data.

13. A method performed by a NAND device, the method comprising:

testing a NAND memory cell of the memory device for an error caused by interrupting a programming of the NAND memory cell by an asynchronous power loss, the testing comprising;

reading the NAND memory cell in a user mode with a first voltage level, the first voltage level being a second voltage level shifted an amount towards a zero voltage level, the second voltage level being a lowest voltage level of a plurality of voltage levels used in a normal read operation on the memory cell;

determining, based upon a value read with the first voltage level, that the cell was incompletely programmed; and

marking the memory cell as incompletely programmed.

14. The method of claim 13, wherein the first voltage level is a voltage level used to read one of:

a least significant bit or a most significant bit stored in the memory cell.

15. The method of claim 13, further comprising:

detecting an asynchronous power loss based upon determining that a shut-down indicator is not present and identifying the memory cell responsive to detecting the asynchronous power loss.

16. The method of claim 15, further comprising:

receiving an indication that a synchronous shut down is in process;

responsive to the indication that the synchronous shut down is in process, setting a shut-down indicator flag;

upon a subsequent power up, detecting that the shut down indicator flag is set; and

responsive to detecting that the shut down indicator flag is set, refraining from testing memory cells.

17. The method of claim 13, wherein the method comprises identifying the memory cell of the memory device by finding a last fully written memory cell.

18. The method of claim 13, wherein the memory cell is capable of storing one of:

2 bits, 3 bits or 4 bits of data.

19. The method of claim 13, wherein the method is performed by a NAND controller.

20. The method of claim 13, wherein the operations comprise erasing the memory cell responsive to marking the memory cell as incompletely programmed.