Structure and method for FinFET device

• US 10,325,816 B2
• Filed: 06/29/2017
• Issued: 06/18/2019
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Fung, Ka-Hing, Chang, Chih-Sheng, Wu, Zhiqiang
• Primary Examiner(s): Landau, Matthew C
• Assistant Examiner(s): Withers, Grant S
• Application Number:
  US15/637,088
• Publication Number:
  US 20170301588A1
• Time in Patent Office: 719 Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 : with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 : Field effect transistors
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 : with at least two independent gates

Abstract

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

Claims

1. A device comprising:

a first fin structure disposed over a substrate, the first fin structure including;

a first semiconductor material layer;

a second semiconductor material layer disposed over the first semiconductor material layer; and

an oxide feature disposed around the first semiconductor material layer; and

a liner disposed along the oxide feature and extending to the second semiconductor material layer; and

a gate structure disposed on the second semiconductor material layer without extending to the liner such that a portion of the second semiconductor material layer is not covered by the gate structure and the liner, wherein the gate structure includes a gate dielectric layer.

2. The device of claim 1, further comprising a shallow trench isolation feature disposed in the substrate adjacent the first fin structure.

3. The device of claim 2, wherein the shallow trench isolation feature physically contacts the second semiconductor material layer.

4. The device of claim 1, wherein the gate structure further includes a gate electrode disposed over the gate dielectric layer.

5. The device of claim 1, wherein the first fin structure further includes a third semiconductor material layer, and

wherein the oxide feature extends from the third semiconductor material layer to the second semiconductor material layer.

6. The device of claim 5, wherein the first semiconductor material layer is disposed over the third semiconductor material layer.

7. The device of claim 1, further comprising a second fin structure, the second fin structure including:

the first semiconductor material layer; and

the second semiconductor material layer disposed over the first semiconductor material layer, and

wherein the first semiconductor material layer is free of any oxide feature being disposed around the first semiconductor material layer.

8. A device comprising:

a first fin structure disposed over a substrate, the first fin structure including;

a first semiconductor material layer;

a second semiconductor material layer disposed over the first semiconductor material layer; and

an oxide feature disposed around the first semiconductor material layer; and

a first liner disposed along the oxide feature and extending to the second semiconductor material layer; and

a device gate that includes a gate dielectric layer disposed on the second semiconductor material layer without extending to the first liner such that a portion of the second semiconductor material layer is not covered by the device gate and the first liner; and

a second fin structure disposed over the substrate, the second fin structure including;

a third semiconductor material layer; and

a fourth semiconductor material layer disposed over the third semiconductor material layer; and

a second liner disposed along the third semiconductor material layer and extending to the fourth semiconductor material layer.

9. The device of claim 8, wherein the first fin structure is part of a first type fin-like field-effect transistor and wherein the second fin structure is part of a second type fin-like field-effect transistor, the first type is opposite the second type.

10. The device of claim 8, wherein the second fin structure further includes a fifth semiconductor material layer, wherein the second liner does not extend to the fifth semiconductor material layer.

11. The device of claim 10, further comprising another gate structure disposed on the fifth semiconductor material layer without extending to the second liner such that a portion of the fourth semiconductor material layer is not covered by the another gate structure and the second liner.

12. The device of claim 8, further comprising a third liner disposed on the first liner along the oxide feature.

13. The device of claim 8, wherein the first semiconductor material layer is formed of the same material as the third semiconductor material layer, and

wherein the second semiconductor material layer is formed of the same material as the fourth semiconductor material layer, and

wherein the first semiconductor material layer is formed of a different material than the second semiconductor material layer.

14. The device of claim 8, wherein the first liner and the second liner are formed of the same material.

15. The device of claim 8, further comprising a shallow trench isolation feature disposed in the substrate adjacent the first fin structure such that the shallow trench isolation feature physically contacts the second semiconductor material layer.

16. A device comprising:

a first fin structure disposed over a substrate, the first fin structure including;

a first semiconductor material layer;

a second semiconductor material layer disposed over the first semiconductor material layer, the second semiconductor material layer being formed of a different material than the first semiconductor material layer; and

an oxide feature disposed directly around the first semiconductor material layer; and

a liner disposed directly on the oxide feature and extending to the second semiconductor material layer such that the liner extends directly on a sidewall of the second semiconductor material layer; and

a dielectric layer disposed directly on the sidewall of the second semiconductor material layer without extending to the liner such that a portion of the sidewall of the second semiconductor material layer is free of both the dielectric layer and the liner.

17. The device of claim 16, further comprising a source/drain feature disposed over the first fin structure.

18. The device of claim 16, wherein the liner includes one or more materials selected from the group consisting of silicon nitride, silicon oxynitride and aluminum oxide.

19. The device of claim 16, further comprising a second fin structure, the second fin structure including:

the first semiconductor material layer; and

the second semiconductor material layer disposed over the first semiconductor material layer; and

wherein the first semiconductor material layer is free of any oxide feature being disposed around the first semiconductor material layer.

20. The device of claim 16, wherein the first fin structure is part of an n-type fin-like field-effect transistor.