Source and drain isolation for CMOS nanosheet with one block mask

• US 10,325,820 B1
• Filed: 01/10/2018
• Issued: 06/18/2019
• Est. Priority Date: 01/10/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Seo, Soon-Cheon, Lee, Choonghyun, Ok, Injo
• Primary Examiner(s): Muse, Ismail A
• Application Number:
  US15/866,851
• Publication Number:
  US 20190214314A1
• Time in Patent Office: 524 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

Claims

1. A method of forming a nanosheet device, the method comprising the steps of:

forming an alternating series of sacrificial and active channel nanosheets as a stack on a substrate;

forming gates on the stack;

forming spacers alongside opposite sidewalls of the gates;

patterning the stack, in between the spacers, into individual PFET and NFET stacks, wherein the patterning forms pockets in the substrate between the PFET and NFET stacks;

laterally recessing the sacrificial nanosheets in the PFET and NFET stacks to expose tips of the active channel nanosheets in the PFET and NFET stacks;

forming inner spacers alongside the PFET and NFET stacks covering the tips of the active channel nanosheets;

forming an oxide protective layer lining the pockets in the substrate;

selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET and NFET stacks,

wherein the step of forming the oxide protective layer comprises the steps of;

growing a silicon germanium (SiGe) layer in the pockets;

depositing a germanium oxide (GeO₂) layer on the SiGe layer; and

annealing the SiGe layer and the GeO₂ layer under conditions sufficient to form a condensed SiGe layer on the SiGe layer, and the oxide protective layer on the condensed SiGe layer.

2. The method of claim 1, wherein the conditions comprise a temperature of from about 400°

C. to about 600°

C., and ranges therebetween.

3. The method of claim 1, wherein the annealing is performed in a nitrogen (N₂) ambient.

4. The method of claim 1, wherein the SiGe layer has a percentage of germanium (Ge) of from about 22% to about 25%, and ranges therebetween.

5. The method of claim 1, wherein the condensed SiGe layer has a percentage of germanium Ge of from about 35% to about 40%, and ranges therebetween.

6. The method of claim 1, wherein the sacrificial nanosheets comprise SiGe and the active channel nanosheets comprise silicon (Si).

7. The method of claim 1, wherein the sacrificial nanosheets comprise Si and the active channel nanosheets comprise SiGe.

8. The method of claim 1, further comprising the steps of:

selectively etching back the inner spacers to expose tips of the active channel nanosheets in the PFET stacks;

epitaxially growing source and drains from the exposed tips of the active channel nanosheets in the PFET stacks;

selectively etching back the inner spacers to expose tips of the active channel nanosheets in the NFET stacks; and

epitaxially growing source and drains from the exposed tips of the active channel nanosheets in the NFET stacks.

9. The method of claim 8, wherein the source and drains epitaxially grown in the PFET stacks comprise SiGe.

10. The method of claim 9, further comprise the steps of:

depositing a second GeO₂ layer on the source and drains epitaxially grown in the PFET stacks; and

annealing the source and drains epitaxially grown in the PFET stacks and the second GeO₂ layer under conditions sufficient to form a second condensed SiGe layer on the source and drains epitaxially grown in the PFET stacks, and a second oxide protective layer on the second condensed SiGe layer.

11. The method of claim 10, wherein the conditions comprise a temperature of from about 400°

C. to about 600°

C., and ranges therebetween.

12. The method of claim 10, wherein the annealing is performed in a N₂ ambient.

13. The method of claim 1, wherein the gates comprise dummy gates, and wherein the method further comprises the steps of:

burying the dummy gates in a dielectric;

removing the dummy gates to form gate trenches in the dielectric;

selectively removing the sacrificial nanosheets from the PFET and NFET stacks within the gate trenches; and

forming replacement gates in the gate trenches, wherein the replacement gates surround at least a portion of each of the active channel nanosheets in a gate-all-around configuration.