Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

• US 10,325,877 B2
• Filed: 04/23/2018
• Issued: 06/18/2019
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Delacruz, Javier A., Awujoola, Abiola, Prabhu, Ashok S., Lattin, Christopher W., Sun, Zhuowen
• Primary Examiner(s): Smith, Courtney L
• Assistant Examiner(s): Ervin, Jessey R
• Application Number:
  US15/959,619
• Publication Number:
  US 20180240773A1
• Time in Patent Office: 421 Days
• Field of Search: None
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1623 the bump connector connecting to a pin of the item
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48108 the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0284 : Details of three-dimensional rigid printed circuit boards H05K1/119 takes precedence; shaping of the substrate H05K3/0014

Abstract

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

Claims

1. A vertically integrated microelectronic package, comprising:

a circuit platform having an upper surface and a lower surface opposite the upper surface thereof, the upper surface of the circuit platform having a wire bond-only surface area;

a first microelectronic device coupled to the upper surface of the circuit platform;

first wire bond wires coupled to and extending away from an upper surface of the first microelectronic device;

second wire bond wires coupled to the upper surface of the circuit platform in the wire bond-only surface area and coupled to the upper surface of the first microelectronic device;

a protective layer disposed over the circuit platform and the first microelectronic device, the protective layer having a lower surface and an upper surface opposite the lower surface thereof with the lower surface of the protective layer being in contact with the upper surface of the circuit platform, the upper surface of the protective layer having a surface mount-only area; and

a second microelectronic device in a face-down orientation coupled to upper ends of the first wire bond wires in the surface mount-only area, the second microelectronic device located above and at least partially overlapping the first microelectronic device.

2. The vertically integrated microelectronic package according to claim 1, further comprising third wire bond wires coupled to and extending away from the upper surface of the circuit platform configured to provide an electric-magnetic interference shield.

3. The vertically integrated microelectronic package according to claim 2, wherein the protective layer is disposed for surrounding at least portions of lengths of the first wire bond wires and the third wire bond wires and for covering the second wire bond wires.

4. The vertically integrated microelectronic package according to claim 2, wherein at least a portion of the surface mount-only area corresponds to the wire bond-only surface area.

5. The vertically integrated microelectronic package according to claim 2, further comprising:

a third microelectronic device coupled to the upper surface of the circuit platform in a face-up orientation in the wire bond-only surface area neighboring the first microelectronic device with a gap therebetween; and

lower ends of the third wire bond wires and the second wire bond wires coupled between the first microelectronic device and the third microelectronic device to the upper surface of the circuit platform.

6. The vertically integrated microelectronic package according to claim 1, wherein the second microelectronic device includes a capacitor of 0.1 or more microfarads.

7. The vertically integrated microelectronic package according to claim 1, wherein the second microelectronic device includes a capacitor coupled to the first microelectronic device for a frequency response of 1 or more GHz.

8. The vertically integrated microelectronic package according to claim 1, wherein each of the second wire bond wires have approximately a nanohenry or less of self-inductance.

9. An inverted vertically integrated microelectronic package, comprising:

a circuit platform having an upper surface and a lower surface opposite the upper surface thereof, the lower surface of the circuit platform having a wire bond-only surface area;

a first microelectronic device coupled to the lower surface of the circuit platform;

first wire bond wires coupled to and extending away from a lower surface of the first microelectronic device;

a protective layer disposed under the circuit platform and the first microelectronic device, the protective layer having a lower surface and an upper surface opposite the lower surface thereof with the upper surface of the protective layer being in contact with the lower surface of the circuit platform, the lower surface of the protective layer having a surface mount-only area;

a second microelectronic device in a face-up orientation coupled to lower ends of the first wire bond wires in the surface mount-only area, the second microelectronic device located below and at least partially underlapping the first microelectronic device; and

second wire bond wires coupled to and extending away from the lower surface of the circuit platform in the wire bond-only surface area and coupled to the lower surface of the first microelectronic device.

10. The inverted vertically integrated microelectronic package according to claim 9, further comprising third wire bond wires coupled to and extending away from the lower surface of the circuit platform configured to provide an electric-magnetic interference shield.

11. The inverted vertically integrated microelectronic package according to claim 10, wherein the protective layer is disposed for surrounding at least portions of lengths of the first wire bond wires and the third wire bond wires and for covering the second wire bond wires.

12. The inverted vertically integrated microelectronic package according to claim 10, wherein:

the protective layer is disposed to cover the lower surface of the first microelectronic device;

the upper surface of the protective layer being in contact with the lower surface of the circuit platform; and

interconnects coupled to the lower ends of the first wire bond wires and the third wire bond wires on the lower surface of the protective layer in the surface mount-only area.

13. The inverted vertically integrated microelectronic package according to claim 10, further comprising:

a third microelectronic device coupled to the lower surface of the circuit platform in a face-down orientation in the wire bond-only surface area neighboring the first microelectronic device with a gap therebetween; and

upper ends of the third wire bond wires and the second wire bond wires coupled between the first microelectronic device and the third microelectronic device to the lower surface of the circuit platform.

14. The vertically integrated microelectronic package according to claim 9, wherein the second microelectronic device includes a capacitor of 0.1 or more microfarads.

15. The vertically integrated microelectronic package according to claim 9, wherein the second microelectronic device includes a capacitor coupled to the first microelectronic device for a frequency response of 1 or more GHz.

16. The vertically integrated microelectronic package according to claim 9, wherein each of the second wire bond wires have approximately a nanohenry or less of self-inductance.

17. A microelectronic component, comprising:

a substrate having a first upper surface;

a conductive layer disposed on the first upper surface including wire bond pads and flip-chip pads respectively having first upper surfaces and second upper surfaces;

a solder mask disposed on the first upper surface between the wire bond pads and the flip-chip pads, the solder mask having a second upper surface disposed above the first upper surfaces and the second upper surfaces;

a eutectic layer disposed on the first upper surfaces and the second upper surfaces; and

first wire bond wires respectively bonded to the wire bond pads to provide an electric-magnetic interference shield.

18. The microelectronic component according to claim 17, wherein the eutectic layer is configured to respectively cover each of the first upper surfaces without extending above the second upper surface of the solder mask.

19. The microelectronic component according to claim 18, wherein the eutectic layer is configured to respectively cover each of the second upper surfaces without extending below the second upper surface of the solder mask.

20. The microelectronic component according to claim 19, further comprising an integrated circuit die flip-chip interconnected with contacts thereof to portions of the eutectic layer corresponding to the second upper surfaces.