Integrated multi-color light-emitting pixel arrays based devices by bonding

• US 10,325,894 B1
• Filed: 04/17/2018
• Issued: 06/18/2019
• Est. Priority Date: 04/17/2018
• Status: Active Grant

• Current Assignee: Shaoher Pan
• Original Assignee: Shaoher Pan
• Inventors: Pan, Shaoher
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US15/955,392
• Time in Patent Office: 427 Days
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/29025 the layer connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/29028 the layer connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/29186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/32146 the layer connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83143 Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83951 Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 2224/83986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 : with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 : with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0549 : being a combination of two or more materials provided in the groups H01L2924/0531 - H01L2924/0546
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1426 : Driver
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 2933/005 : relating to encapsulations
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 : within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01L 33/42 : Transparent materials
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Integrated active-matrix multi-color light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. An example integrated device includes a backplane device and different color light emitting diodes (LEDs) devices arranged in different height planar layers on the backplane device. The backplane device includes at least one backplane having a number of pixel circuits. Each LED device includes an array of LEDs each operable to emit light with a particular color and conductively coupled to respective pixel circuits in the backplane to form active-matrix LED sub-pixels. The different color LED sub-pixels form an array of active-matrix multi-color display pixels. Plug vias can be arranged in different planar layers to conductively couple upper-level LEDs to respective pixel circuits in respective regions over the backplane device. The plug vias can extend from an upper planar layer into a lower planar layer to fix the two planar layers together.

Claims

1. An integrated device comprising:

a backplane device including at least one backplane having a plurality of pixel circuits;

a first planar layer on the backplane device, the first planar layer including;

a plurality of first light emitting elements in a first region over the backplane device, wherein each of the first light emitting elements is operable to emit light with a first color and conductively coupled to a respective pixel circuit in the first region to thereby form a plurality of first light emitting sub-pixels, and

a plurality of first plug vias in a remaining region over the backplane device, the remaining region being non-overlapping with the first region, wherein each of the first plug vias is conductively coupled to a respective pixel circuit in the remaining region; and

a second planar layer on the first planar layer, the second planar layer including

a plurality of second light emitting elements on respective first plug vias in a second region over the backplane device, the second region being in the remaining region, wherein each of the second light emitting elements is operable to emit light with a second color different from the first color and conductively coupled to a respective pixel circuit in the second region through a respective first plug via on the second region to thereby form a plurality of second light emitting sub-pixels.

2. The integrated device of claim 1, wherein the second planar layer further includes:

a plurality of second plug vias on respective first plug vias in a third region of the backplane device, the third region being in the remaining region and non-overlapping with the second region, wherein each of the second plug vias is conductively coupled to a respective pixel circuit in the third region through a respective first plug vias,

wherein the integrated device further comprises a third planar layer on the second planar layer, the third planar layer including

a plurality of third light emitting elements in the third region, wherein each of the third light emitting elements is operable to emit light with a third color different from the first color and the second color, and wherein each of the third light emitting elements is conductively coupled to a respective pixel circuit in the third region through a respective first plug via and a respective second plug via in the third region to thereby form a plurality of third light emitting sub-pixels, and

wherein the plurality of first light emitting sub-pixels, the plurality of second light emitting sub-pixels, and the plurality of third light emitting sub-pixels form an array of multi-color light emitting pixels.

3. The integrated device of claim 2, wherein the first, second, and third colors comprise red, blue, and green.

4. The integrated device of claim 2, wherein each of the multi-color light emitting pixels comprises at least one first light emitting element, at least one second light emitting element, and at least one third light emitting element and respective pixel circuits coupled to the first, second, third light emitting elements, and

wherein the first, second, and third light emitting elements in the multi-color light emitting pixel are adjacent to each other.

5. The integrated device of claim 2, wherein each of the pixel circuits is coupled to a respective driver electrode in a top layer of the backplane device,

wherein each of the first plug vias extends into a respective driver electrode in the remaining region, such that the first plug via is anchored in the respective driver electrode, and

wherein each of the second plug vias extends into a respective first plug vias in the third region, such that the second plug via is anchored in the respective first plug via.

6. The integrated device of claim 1, wherein each of the pixel circuits is coupled to a respective driver electrode in a top layer of the backplane device,

wherein each of the first light emitting elements comprises one or more first quantum well layers between a first top contact electrode and a first bottom contact electrode,

wherein the first top contact electrodes of the first light emitting elements are conductively connected by one or more first conductive lines as one or more first common electrodes, and

wherein the first bottom contact electrode of each of the first light emitting elements is bonded to a respective driver electrode through a respective first intermediate conductive layer, and each of the first light-emitting elements has a size same as the respective first intermediate conductive layer and is self-aligned with the respective first intermediate conductive layer.

7. The integrated device of claim 6, wherein each of the second light emitting elements comprises one or more second quantum well layers between a second top contact electrode and a second bottom contact electrode,

wherein the second top contact electrodes of the second light emitting elements are conductively connected by one or more second conductive lines as one or more second common electrodes, and

wherein the second bottom contact electrode of each of the second light emitting elements is bonded to a respective first plug via through a respective second intermediate conductive layer, and each of the second light-emitting elements has a size same as the respective second intermediate conductive layer and is self-aligned with the respective second intermediate conductive layer.

8. The integrated device of claim 7, wherein each of the first intermediate conductive layers, the second intermediate conductive layers, the first conductive lines, and the second conductive lines is made of transparent ITO metal material.

9. The integrated device of claim 1, wherein each of the pixel circuits is coupled to a respective driver electrode in a top layer of the backplane device,

wherein each of the first plug vias is on a respective driver electrode in the remaining region and conductively coupled to the respective driver electrode, and

wherein each of the first plug vias has a size on a top surface no larger than a size of a respective second light-emitting elements and a size a bottom surface no larger than the respective driver electrode in the second region.

10. The integrated device of claim 1, further comprising:

isolation material between adjacent first light emitting elements, between adjacent first plug vias, between adjacent first emitting elements and first plug vias, and between adjacent second light emitting elements.

11. The integrated device of claim 1, wherein each of the pixel circuits comprises a non-volatile memory conductively coupled to a corresponding driver electrode in a top layer of the backplane,

wherein the backplane comprises scanning drivers and data drivers, and each of the non-volatile memories is coupled to one of the scanning drivers through at least one word line and to one of the data drivers through at least one bit line, and

wherein each of the first light emitting elements is conductively coupled to a respective non-volatile memory in the first region through a corresponding driver electrode in the first region, and wherein each of the second light emitting elements is conductively coupled to a respective non-volatile memory in the second region through a respective first plug via and a corresponding driver electrode in the second region, the respective first plug via being in touch with the corresponding driver electrode and conductively coupled to the corresponding driver electrode.

12. The integrated device of claim 11, wherein the transparent protective layer is touch-sensitive, and configured to form, together with one or more first common electrodes of the first light-emitting elements and one or more second common electrodes of the second light-emitting elements, a capacitive touch screen position sensor.

13. The integrated device of claim 1, further comprising:

a polarizer film on the array of multi-color light-emitting pixels; and

a transparent protective layer on the polarizer film.

14. The integrated device of claim 1, wherein the backplane comprises a low temperature polysilicon (LTPS) thin-film transistors (TFT) array control backplane.

15. The integrated device of claim 14, wherein each of the pixels includes at least one of:

a size less than 10 μ

m,

a respond time faster than 1.0 μ

s, or

an emitting light flux higher than 10 cd/mm^2.

16. The integrated device of claim 14, comprising at least one of:

a thickness less than 1.0 mm, or

a device area larger than 100 mm×

100 mm.

17. The integrated device of claim 14, wherein the device is flexible, rollable, and foldable.

18. The integrated device of claim 1, wherein the backplane is operable to drive the array of multi-color light emitting pixels by pulse-width-modulation (PWM).

19. The integrated device of claim 1, wherein each of the multi-color light-emitting pixels includes at least one first sub-pixel and at least one second sub-pixel having respective first and second light brilliances to emit the first color and the second color, and

wherein the backplane is configured to drive the first and second sub-pixels with respective first and second currents, and a current ratio between the first and second currents is based on a ratio between the first and second light brilliances.

20. An integrated device comprising:

a backplane device including at least one backplane having a plurality of pixel circuits;

a first light emitting device arranged in a first planar layer on the backplane device, the first light emitting device including a plurality of first light emitting elements each conductively coupled to respective pixel circuits in the backplane device to form an array of first light emitting pixels, each of the first light emitting elements being operable to emit light with a first wavelength; and

a second light emitting device arranged in a second planar layer higher than the first planar layer relative to the backplane device, the second light emitting device including a plurality of second light emitting elements each conductively coupled to respective pixel circuits in the backplane device to form an array of second light emitting pixels, each of the second light emitting element being operable to emit light with a second wavelength different from the first wavelength.

21. The integrated device of claim 20, further comprising:

a third light emitting device arranged in a third planar layer higher than the second planar layer relative to the backplane device, the third light emitting device including a plurality of third light emitting elements each conductively coupled to respective pixel circuits in the backplane device to form an array of third light emitting pixels, each of the third light emitting element being operable to emit light with a third wavelength different from the first wavelength and the second wavelength,

wherein the array of first light emitting pixels, the array of second light emitting pixels, and the array of third light emitting pixels form an array of multi-color light emitting pixels.

22. The integrated device of claim 20, wherein the second light emitting elements are vertically higher than the first light emitting elements, such that there is substantially no cross-talk at least in a horizontal direction between the light emitted from the second light emitting elements and the light emitted from the first light emitting elements.

23. The integrated device of claim 20, configured to be a three-dimensional (3D) light emitting device with light emitting elements with different wavelengths in planar layers at different heights from the backplane device.

24. The integrated device of claim 20, further comprising:

a plurality of plug vias formed in the first planar layer and separated from the first light emitting elements,

wherein each of the plug vias is arranged between a respective second light emitting element and a respective pixel circuit for the respective second light emitting element and conductively couples the respective second light emitting element to the respective pixel circuit.

25. The integrated device of claim 24, wherein each of the plug vias extends through the first planar layer into the respective pixel circuit in the backplane device and is anchored into the respective pixel circuit, such that the first planar layer is fixed together with the backplane device by the plug vias.

26. The integrated device of claim 20, further comprising:

a plurality of plug vias formed in the second planar layer and separated from the second light emitting elements,

wherein each of the plug vias extends through the second planar layer into the first planar layer and is anchored into the first planar layer, such that the second planar layer is fixed together with the first planar layer by the plug vias, and

wherein the plug vias are anchored into an area of the first planar layer that non-overlaps with an area including the first light emitting elements.

27. The integrated device of claim 26, wherein each of the plug vias extends through the second planar layer and the first planar layer into the backplane device and is anchored into the backplane device, such that the second planar layer and the first planar layer are fixed together with the backplane device by the plug vias.

28. An integrated device comprising:

a backplane device including at least one backplane having a plurality of pixel circuits;

a light emitting device arranged in a planar layer on the backplane device, the light emitting device including a plurality of light emitting elements each conductively coupled to respective pixel circuits in the backplane device to form an array of light emitting pixels; and

a plurality of plug vias penetrating through the planar layer into the backplane device such that the plug vias are anchored in the backplane device, such that the light emitting device is fixed onto the backplane device.