ROM chip manufacturing structures having shared gate electrodes

• US 10,325,909 B2
• Filed: 02/12/2018
• Issued: 06/18/2019
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/894,138
• Publication Number:
  US 20180175026A1
• Time in Patent Office: 491 Days
• Field of Search: 365 94
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

Claims

1. A device comprising:

a read only memory (ROM) array comprising ROM cells arranged in a plurality of rows and a plurality columns, wherein a first row of the plurality of rows comprises;

first ROM cells sharing a first gate electrode electrically connected to a word line; and

second ROM cells sharing a second gate electrode physically separated from the first gate electrode, wherein the second gate electrode is electrically connected to the word line, wherein a total number ROM cells sharing the first gate electrode is equal to a total number of ROM cells sharing the second gate electrode, and wherein the first row runs in a direction substantially parallel to a lengthwise direction of the first gate electrode and the second gate electrode.

2. The device of claim 1, further comprising:

a first gate contact electrically connecting the first gate electrode and the second gate electrode to the word line, wherein the first gate contact physically contacts the first gate electrode and the second gate electrode.

3. The device of claim 1, further comprising:

a first gate contact physically contacting the first gate electrode;

a second gate contact physically contacting the second gate electrode; and

a conductive line electrically connecting the first gate contact and the second gate contact to the word line.

4. The device of claim 1, further comprising:

a third gate electrode permanently connected to ground, wherein the third gate electrode is partially disposed in the first ROM cells and the second ROM cells.

5. The device of claim 1, further comprising:

a third gate electrode permanently connected to ground, wherein the third gate electrode is at least partially disposed in the first ROM cells; and

a fourth gate electrode permanently connected to ground, wherein the fourth gate electrode is physically separated from the third gate electrode and is at least partially disposed in the second ROM cells.

6. The device of claim 1, further comprising:

a strap cell disposed between the first ROM cells and the second ROM cells, wherein a first endpoint of the first gate electrode and a second endpoint of the second gate electrode are disposed in the strap cell.

7. A method comprising:

forming a first gate structure in a read only memory (ROM) array row, wherein the ROM array row runs in a direction substantially parallel to the first gate structure;

forming a second gate structure in the ROM array row, wherein the second gate structure is physically separated from the first gate structure, and wherein a total number of first ROM cells sharing the first gate structure is equal to a total number of second ROM cells sharing the second gate structure; and

electrically connecting the first gate structure and the second gate structure to a common word line.

8. The method of claim 7, wherein electrically connecting the first gate structure and the second gate structure to the common word line comprises:

physically connecting a first via to the first gate structure; and

physically connecting a second via to the second gate structure, wherein an insulating material is disposed between the first via and the second via.

9. The method of claim 7, wherein electrically connecting the first gate structure and the second gate structure to the common word line comprises:

physically connecting a via to both the first gate structure and the second gate structure.

10. The method of claim 7, wherein forming the first gate structure and forming the second gate structure comprises:

forming the first gate structure and the second gate structure to have substantially uniform lengths.

11. The method of claim 7, further comprising:

forming a third gate structure extending through the first ROM cells and the second ROM cells; and

permanently electrically connecting the third gate structure to electrical ground.

12. The method of claim 7, further comprising:

forming a third gate structure extending through the first ROM cells; and

forming a fourth gate structure extending through the second ROM cells, wherein the third gate structure and the fourth gate structure are physically separated; and

permanently electrically connecting the third gate structure and the fourth gate structure to electrical ground.

13. The method of claim 7, wherein a first endpoint of the first gate structure and a second endpoint of the second gate structure are disposed in a third ROM cell.

14. A device comprising:

a plurality of first read only memory (ROM) cells in a first row of a ROM array;

a first gate electrode extending through the first ROM cells in a direction substantially parallel to the first row of the ROM array;

a plurality of second ROM cells in the first row of the ROM array;

a second gate electrode extending through the second ROM cells in a direction substantially parallel to the first row of the ROM array, a total number of the first ROM cells sharing the first gate electrode being equal to a total number of the second ROM cells sharing the second gate electrode; and

a strap cell disposed between the first ROM cells and the second ROM cells.

15. The device of claim 14, wherein a first endpoint of the first gate electrode and a second endpoint of the second gate electrode are disposed in the strap cell.

16. The device of claim 14, further comprising:

an isolation device extending through the first ROM cells, the second ROM cells, and the strap cell, the isolation device having an uninterrupted gate electrode permanently connected to ground.

17. The device of claim 14, further comprising:

a common word line connected to the first gate electrode and the second gate electrode.

18. The device of claim 17, further comprising:

a first via connecting the common word line to the first gate electrode;

a second via connecting the common word line to the second gate electrode; and

an insulating material is disposed between the first via and the second via.

19. The device of claim 17, further comprising:

a first via connecting the common word line to both the first gate electrode and the second gate electrode.

20. The device of claim 17, wherein the first gate electrode and the second gate electrode have substantially uniform lengths.