Accommodating imperfectly aligned memory holes

• US 10,325,923 B2
• Filed: 02/07/2018
• Issued: 06/18/2019
• Est. Priority Date: 02/08/2017
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Purayath, Vinod R.
• Primary Examiner(s): Harriston, William A
• Application Number:
  US15/891,126
• Publication Number:
  US 20180226426A1
• Time in Patent Office: 496 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. The methods further include placing sacrificial polysilicon around the memory hole before forming the bottom stack and removing the sacrificial polysilicon from the slit trench to allow a conducting gapfill to make electrical contact to the polysilicon inside the memory hole.

Claims

1. A method of forming a 3-d flash memory cell, the method comprising:

forming an etch stop layer on a substrate;

forming a sacrificial polysilicon layer on the etch stop layer;

forming a bottom portion of a compound stack of alternating silicon oxide and silicon nitride slabs and forming a bottom portion of a memory hole through the bottom portion of the compound stack;

forming a top portion of the compound stack of alternating silicon oxide and silicon nitride slabs and forming a top portion of a memory hole through the top portion of the compound stack, wherein the bottom portion and the top portion of the compound stack are fluidly coupled and the top portion is laterally displaced from the bottom portion;

forming a conformal charge-trap layer on the top portion and the bottom portion of the memory hole;

forming a conformal polysilicon layer on the conformal charge-trap layer;

filling the memory hole with dielectric and capping the dielectric with a polysilicon plug and forming a mask above the polysilicon plug;

patterning the mask and etching a vertical slit trench next to the memory hole to expose the etch stop layer and leave a remaining portion of the sacrificial polysilicon layer;

replacing the silicon nitride slabs in each of the top portion and the bottom portion of the compound stack with a conductor;

exposing the conformal charge-trap layer by removing the remaining portion of the sacrificial polysilicon layer to form an exposed portion of the conformal charge-trap layer;

exposing the conformal polysilicon layer by removing the exposed portion of the conformal charge-trap layer; and

depositing gapfill polysilicon in the vertical slit trench, wherein the gapfill polysilicon makes electrical contact with the remaining portion of the conformal polysilicon layer.

2. The method of claim 1 wherein the conformal charge-trap layer is an ONO layer comprising a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.

3. The method of claim 1 wherein the top portion is laterally displaced from the bottom portion by at least 5 nm.

4. The method of claim 1 wherein the etch stop layer comprises aluminum oxide.

5. The method of claim 1 wherein the conductor is tungsten.

6. The method of claim 1 wherein removing the remaining portion of the sacrificial polysilicon layer comprises a gas-phase etch.

7. The method of claim 1 wherein removing the exposed portion of the conformal charge-trap layer is performed by exciting a hydrogen-containing precursor and a fluorine-containing precursor in a remote plasma to form plasma effluents.

8. The method of claim 7 wherein the plasma effluents are flowed into a substrate processing region through a showerhead, wherein the substrate is in the substrate processing region and a temperature of the substrate is greater than 95°

C.

9. A method of forming a 3-d flash memory cell, the method comprising:

forming an etch stop layer on a substrate;

forming a polysilicon layer on the etch stop layer;

forming a bottom portion of a compound stack of alternating silicon oxide and silicon nitride slabs and forming a bottom portion of a memory hole through the bottom portion of the compound stack;

forming a top portion of the compound stack of alternating silicon oxide and silicon nitride slabs and forming a top portion of a memory hole through the top portion of the compound stack, wherein the bottom portion and the top portion of the compound stack are fluidly coupled and the top portion is misaligned relative to the bottom portion by a lateral displacement;

forming a conformal charge-trap layer on the top portion and the bottom portion of the memory hole;

forming a conformal polysilicon layer on the conformal charge-trap layer;

filling the memory hole with dielectric and capping the dielectric with a polysilicon plug;

exposing the etch stop layer by directionally etching a vertical slit trench next to the memory hole, wherein exposing the etch stop layer leaves a remaining portion of the polysilicon layer and the remaining portion of the polysilicon layer surrounds the bottom portion of the compound stack;

exposing the conformal charge-trap layer by removing the remaining portion of the polysilicon layer, wherein exposing the conformal charge-trap layer forms an exposed portion of the conformal charge-trap layer;

exposing the conformal polysilicon layer by removing the exposed portion of the conformal charge-trap layer; and

depositing gapfill polysilicon in the vertical slit trench, wherein the gapfill polysilicon makes electrical contact with the remaining portion of the conformal polysilicon layer.

10. The method of claim 9 wherein directionally etching the vertical slit trench comprises reactive ion etching.

11. The method of claim 9 wherein removing the remaining portion of the polysilicon layer comprises isotropically etching with a gas-phase etch.

12. The method of claim 9 wherein the lateral displacement is 5 nm or more.

13. The method of claim 9 wherein removing the remaining portion of the polysilicon layer comprises exciting both a fluorine precursor and a hydrogen precursor in a remote plasma to form plasma effluents and flowing the plasma effluents into a substrate processing region housing the substrate.

14. The method of claim 9 wherein removing the exposed portion of the conformal charge-trap layer is performed by:

1) exposing the substrate to a combination of moisture and radical-fluorine to remove an outer silicon oxide layer of the conformal charge-trap layer,

2) exposing the substrate to plasma effluents formed from a fluorine-containing precursor and oxygen-containing precursor in a remote plasma to remove a silicon nitride layer of the conformal charge-trap layer, and

3) exposing the substrate to a combination of moisture and radical-fluorine to remove an inner silicon oxide layer of the conformal charge-trap layer.

15. The method of claim 9 wherein the conformal charge-trap layer is continuous around the memory hole prior to removing the exposed portion of the conformal charge-trap layer.

16. The method of claim 9 wherein the conformal polysilicon layer is continuous around the memory hole.