Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures

• US 10,325,926 B2
• Filed: 03/20/2017
• Issued: 06/18/2019
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Zhang, Ming, Bayless, Andrew M., Zahurak, John K.
• Primary Examiner(s): Malsawma, Lex H
• Assistant Examiner(s): Jones, Eric W
• Application Number:
  US15/464,060
• Publication Number:
  US 20170194351A1
• Time in Patent Office: 820 Days
• Field of Search: 257348, 257629, 257632, 257646, 438406
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.

Claims

1. A semiconductor-metal-on-insulator structure comprising:

an insulator material on a first semiconductor substrate;

an amorphous germanium material bonded to the insulator material;

a conductive material over and in direct physical contact with the amorphous germanium material, the conductive material comprising one or more members of the group consisting of phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride and tungsten oxide; and

a second semiconductor substrate over the conductive material.

2. A semiconductor-metal-on-insulator structure comprising:

an insulator material on a first semiconductor substrate;

a conductive material over the insulator material, the conductive material comprising one or more members of the group consisting of phase change material and tungsten;

an amorphous silicon material over the conductive material; and

a second semiconductor substrate over the conductive material.

3. The semiconductor-metal-on-insulator structure of claim 2, further comprising a bonding material disposed between the conductive material and the amorphous silicon material.

4. The semiconductor-metal-on-insulator structure of claim 3, wherein the bonding material comprises at least one of an additional amorphous silicon material and an oxide material.

5. A semiconductor-metal-on-insulator structure comprising:

an insulator material on a first semiconductor substrate;

a conductive material over the insulator material;

a first portion of an epitaxial silicon material and a second portion of a silicon-germanium material, the first and second portions being discrete portions and having an interface there between, the first portion or the second portion being bonded to the insulator material; and

a second semiconductor substrate over the conductive material.

6. The semiconductor-metal-on-insulator structure of claim 5, wherein the insulator material comprises an oxide material having an amorphous silicon material formed thereon.

7. A method for fabricating a semiconductor-metal-on-insulator structure, comprising:

forming an acceptor wafer comprising an insulator material formed over a first semiconductor substrate;

forming a donor wafer comprising a conductive material over a precursor semiconductor substrate, an amorphous silicon material over the conductive material, and an implanted zone within the precursor semiconductor substrate, the conductive material comprising one or more members of the group consisting of phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride and tungsten oxide;

positioning the amorphous silicon material of the donor wafer in direct physical contact with the insulator material of the acceptor wafer and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer; and

removing a portion of the precursor semiconductor substrate proximate the implanted zone within the precursor semiconductor substrate.

8. The method of claim 7, further comprising treating at least one of a surface of the amorphous silicon material and a surface of the insulator material with a chemical, a plasma, or an implant activation before bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer.

9. The method of claim 7, wherein forming an acceptor wafer comprising an insulator material formed over a first semiconductor substrate comprises forming an oxide material over a first semiconductor substrate comprising crystalline silicon.

10. The method of claim 7, wherein forming a donor wafer comprising a conductive material over a precursor semiconductor substrate, an amorphous silicon material over the conductive material, and an implanted zone within the precursor semiconductor substrate comprises forming a conductive material over a crystalline silicon substrate, an amorphous silicon material over the conductive material, and a hydrogen-implanted zone within the crystalline silicon substrate.

11. The method of claim 7, wherein forming a donor wafer further comprises forming a dielectric material between the conductive material and the precursor semiconductor substrate.

12. The method of claim 7, wherein forming a donor wafer comprising a conductive material over a precursor semiconductor substrate comprises forming a non-reactive conductive material over the precursor semiconductor substrate and a reactive conductive material over the non-reactive conductive material and reacting the reactive conductive material with the amorphous silicon material of the donor wafer to form a conductive silicide material.

13. The method of claim 7, wherein forming the conductive material over the precursor semiconductor substrate comprises:

depositing the conductive material over the precursor semiconductor substrate;

forming a cap material over the conductive material;

patterning the cap material and the conductive material; and

forming a dielectric material between adjacent portions of the patterned cap material and patterned conductive material.

14. The method of claim 7, wherein forming the donor wafer further comprises forming at least one portion of an epitaxial silicon material and at least one portion of a silicon-germanium material between the conductive material and the amorphous silicon material.

15. The method of claim 7, wherein forming the donor wafer further comprises forming at least one portion of an oxide material and at least one portion of a nitride material between the conductive material and the amorphous silicon material.

16. A method of fabricating a semiconductor device, comprising:

forming an acceptor wafer comprising an insulator material formed over a first semiconductor substrate;

forming a donor wafer comprising a conductive material over a precursor semiconductor substrate, an amorphous silicon material over the conductive material, and an implanted zone within the precursor semiconductor substrate, the conductive material comprising one or more members of the group consisting of phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride and tungsten oxide;

positioning the amorphous silicon material of the donor wafer in direct physical contact with the insulator material of the acceptor wafer and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer;

removing a portion of the precursor semiconductor substrate proximate the implanted zone to form a second semiconductor substrate; and

fabricating at least one memory cell on the second semiconductor substrate.

17. The method of claim 16, further comprising patterning the conductive material to form at least one of a buried word line and a buried bit line.

18. The method of claim 16, wherein fabricating at least one memory cell on the second semiconductor substrate comprises:

forming an active area from a portion of the second semiconductor substrate substantially surrounded on the sides and bottom by an additional insulator material;

forming a high-k gate dielectric and a metal gate on the active area; and

forming a source region and a drain region in the active area.

19. The method of claim 16, wherein fabricating at least one memory cell on the second semiconductor substrate comprises:

etching the second semiconductor substrate to form at least one pillar;

forming a source region, an active area, and a drain region in the at least one pillar; and

forming a gate dielectric and a gate on the active area.

20. The method of claim 16, wherein fabricating at least one memory cell on the second semiconductor substrate comprises:

forming a diode in the second semiconductor substrate; and

forming a bottom electrode, a memory medium, and a top electrode on the diode.