Advanced transistors with punch through suppression

• US 10,325,986 B2
• Filed: 10/20/2016
• Issued: 06/18/2019
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Shifren, Lucian, Ranade, Pushkar, Gregory, Paul E., Sonkusale, Sachin R., Zhang, Weimin, Thompson, Scott E.
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US15/298,913
• Publication Number:
  US 20170040419A1
• Time in Patent Office: 971 Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10¹⁸ dopant atoms per cm³. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Claims

1. A field effect transistor structure having a gate dielectric under a gate with length Lg, comprising:

a substrate,

a well in the substrate doped to have a first concentration of a first conductivity type dopant,

a substantially undoped channel under the gate dielectric and extending to a source and a drain, the source and the drain being doped to have a second conductivity type dopant different from the first conductivity type dopant, the substantially undoped channel having a second concentration of the first conductivity type dopant less than the first concentration,

a screening region positioned above the well and under the gate dielectric, the screening region extending to the source and drain and having a third concentration of the first conductivity type dopant, the screening region setting a depth of a depletion region below the gate in a direction from the substantially undoped channel toward the screening region, a ratio of the third concentration to the second concentration being more than ten, a profile of the first conductivity type dopant having a peak in the screening region,

at least one punch through suppression region having a fourth concentration of the first conductivity type dopant intermediate between the first concentration and the third concentration, with the punch through suppression region positioned above the well and beneath the screening region, and

a threshold voltage set region having a fifth concentration of the first conductivity type dopant intermediate between the second concentration and the third concentration, with the threshold voltage set region positioned under the substantially undoped channel and above the screening region, the threshold voltage set region extending to the source and drain.

2. The field effect transistor structure of claim 1, wherein the screening region is positioned at a depth below the gate dielectric of between about Lg/5 and about Lg/1.

3. The field effect transistor structure of claim 1, wherein the channel is formed as a blanket epitaxial layer.

4. The field effect transistor structure of claim 1, wherein the punch through suppression region has a dopant concentration different from the screening region.

5. The field effect transistor structure of claim 1, wherein each of the screening region and the punch through suppression region establishes a notch in the profile of the first conductivity type dopant.

6. The field effect transistor structure of claim 1, wherein the third concentration is larger than the fourth concentration and the fifth concentration, the fourth concentration is larger than the first concentration.

7. The field effect transistor structure of claim 1, wherein the depletion region does not go through the screening region, regardless of a voltage of the well when a voltage of the gate equals to the threshold voltage.

8. The field effect transistor structure of claim 1, wherein there is not a local minimum between the threshold voltage set region and the screening region in the profile of the first conductivity type dopant.