Spin transfer torque cell for magnetic random access memory

• US 10,326,074 B2
• Filed: 08/08/2017
• Issued: 06/18/2019
• Est. Priority Date: 06/24/2011
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Gaidis, Michael C., Nowak, Janusz J., Worledge, Daniel C.
• Primary Examiner(s): Nguyen, Cuong Q
• Application Number:
  US15/671,847
• Publication Number:
  US 20170338407A1
• Time in Patent Office: 679 Days
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H01F 41/307 insulating or semiconductive spacer
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Claims

1. A method for manufacturing a spin transfer torque (STT) magnetic random access memory (MRAM) device, the method comprising:

forming at least one conductive via over a first electrode;

forming a first insulator over the first electrode;

forming a second insulator over the first insulator, where the first and second insulators contact the at least one conductive via;

depositing over the at least one conductive via and the second insulator a magnetic tunnel junction (MTJ) stack including at least a free layer; and

forming a seed layer directly between the at least one conductive via and the free layer of the MTJ stack, the free layer including an excess agent;

wherein the second insulator delivers the excess agent to enable a chemical reaction between the free layer of the MTJ stack and the second insulator.

2. The method of claim 1, further comprising depositing a second electrode over the MTJ stack.

3. The method of claim 2, further comprising annealing the MRAM device to cause the at least one conductive via to absorb the excess agent.

4. The method of claim 1, wherein the first insulator has a first thickness and the second insulator has a second thickness, the first thickness being greater than the second thickness.

5. The method of claim 1, wherein the seed layer contacts the second insulator.

6. The method of claim 1, wherein the seed layer extends a length of the free layer of the MTJ stack.

7. The method of claim 1, wherein the seed layer extends over an entire upper surface of the second insulator.

8. The method of claim 1, wherein the excess agent is selected from the group consisting of elements from the thirteenth, fifteenth, sixteenth and seventeenth columns of the periodic table of elements.

9. The method of claim 1, wherein annealing causes the excess agent to react with the free layer to increase a resistivity of portions of the free layer that are above the excess agent.